cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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usb.txt (1391B)


      1Freescale QUICC Engine USB Controller
      2
      3Required properties:
      4- compatible : should be "fsl,<chip>-qe-usb", "fsl,mpc8323-qe-usb".
      5- reg : the first two cells should contain usb registers location and
      6  length, the next two two cells should contain PRAM location and
      7  length.
      8- interrupts : should contain USB interrupt.
      9- fsl,fullspeed-clock : specifies the full speed USB clock source:
     10  "none": clock source is disabled
     11  "brg1" through "brg16": clock source is BRG1-BRG16, respectively
     12  "clk1" through "clk24": clock source is CLK1-CLK24, respectively
     13- fsl,lowspeed-clock : specifies the low speed USB clock source:
     14  "none": clock source is disabled
     15  "brg1" through "brg16": clock source is BRG1-BRG16, respectively
     16  "clk1" through "clk24": clock source is CLK1-CLK24, respectively
     17- hub-power-budget : USB power budget for the root hub, in mA.
     18- gpios : should specify GPIOs in this order: USBOE, USBTP, USBTN, USBRP,
     19  USBRN, SPEED (optional), and POWER (optional).
     20
     21Example:
     22
     23usb@6c0 {
     24	compatible = "fsl,mpc8360-qe-usb", "fsl,mpc8323-qe-usb";
     25	reg = <0x6c0 0x40 0x8b00 0x100>;
     26	interrupts = <11>;
     27	interrupt-parent = <&qeic>;
     28	fsl,fullspeed-clock = "clk21";
     29	gpios = <&qe_pio_b  2 0 /* USBOE */
     30		 &qe_pio_b  3 0 /* USBTP */
     31		 &qe_pio_b  8 0 /* USBTN */
     32		 &qe_pio_b  9 0 /* USBRP */
     33		 &qe_pio_b 11 0 /* USBRN */
     34		 &qe_pio_e 20 0 /* SPEED */
     35		 &qe_pio_e 21 0 /* POWER */>;
     36};