cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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fsl,imx8mm-vpu-blk-ctrl.yaml (1671B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: NXP i.MX8MM VPU blk-ctrl
      8
      9maintainers:
     10  - Lucas Stach <l.stach@pengutronix.de>
     11
     12description:
     13  The i.MX8MM VPU blk-ctrl is a top-level peripheral providing access to
     14  the NoC and ensuring proper power sequencing of the VPU peripherals
     15  located in the VPU domain of the SoC.
     16
     17properties:
     18  compatible:
     19    items:
     20      - const: fsl,imx8mm-vpu-blk-ctrl
     21      - const: syscon
     22
     23  reg:
     24    maxItems: 1
     25
     26  '#power-domain-cells':
     27    const: 1
     28
     29  power-domains:
     30    minItems: 4
     31    maxItems: 4
     32
     33  power-domain-names:
     34    items:
     35      - const: bus
     36      - const: g1
     37      - const: g2
     38      - const: h1
     39
     40  clocks:
     41    minItems: 3
     42    maxItems: 3
     43
     44  clock-names:
     45    items:
     46      - const: g1
     47      - const: g2
     48      - const: h1
     49
     50required:
     51  - compatible
     52  - reg
     53  - power-domains
     54  - power-domain-names
     55  - clocks
     56  - clock-names
     57
     58additionalProperties: false
     59
     60examples:
     61  - |
     62    #include <dt-bindings/clock/imx8mm-clock.h>
     63    #include <dt-bindings/power/imx8mm-power.h>
     64
     65    vpu_blk_ctrl: blk-ctrl@38330000 {
     66      compatible = "fsl,imx8mm-vpu-blk-ctrl", "syscon";
     67      reg = <0x38330000 0x100>;
     68      power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>,
     69                      <&pgc_vpu_g2>, <&pgc_vpu_h1>;
     70      power-domain-names = "bus", "g1", "g2", "h1";
     71      clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>,
     72               <&clk IMX8MM_CLK_VPU_G2_ROOT>,
     73               <&clk IMX8MM_CLK_VPU_H1_ROOT>;
     74      clock-names = "g1", "g2", "h1";
     75      #power-domain-cells = <1>;
     76    };