fsl,imx8mn-disp-blk-ctrl.yaml (2585B)
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: NXP i.MX8MN DISP blk-ctrl 8 9maintainers: 10 - Lucas Stach <l.stach@pengutronix.de> 11 12description: 13 The i.MX8MN DISP blk-ctrl is a top-level peripheral providing access to 14 the NoC and ensuring proper power sequencing of the display and MIPI CSI 15 peripherals located in the DISP domain of the SoC. 16 17properties: 18 compatible: 19 items: 20 - const: fsl,imx8mn-disp-blk-ctrl 21 - const: syscon 22 23 reg: 24 maxItems: 1 25 26 '#power-domain-cells': 27 const: 1 28 29 power-domains: 30 minItems: 5 31 maxItems: 5 32 33 power-domain-names: 34 items: 35 - const: bus 36 - const: isi 37 - const: lcdif 38 - const: mipi-dsi 39 - const: mipi-csi 40 41 clocks: 42 minItems: 11 43 maxItems: 11 44 45 clock-names: 46 items: 47 - const: disp_axi 48 - const: disp_apb 49 - const: disp_axi_root 50 - const: disp_apb_root 51 - const: lcdif-axi 52 - const: lcdif-apb 53 - const: lcdif-pix 54 - const: dsi-pclk 55 - const: dsi-ref 56 - const: csi-aclk 57 - const: csi-pclk 58 59required: 60 - compatible 61 - reg 62 - power-domains 63 - power-domain-names 64 - clocks 65 - clock-names 66 67additionalProperties: false 68 69examples: 70 - | 71 #include <dt-bindings/clock/imx8mn-clock.h> 72 #include <dt-bindings/power/imx8mn-power.h> 73 74 disp_blk_ctl: blk_ctrl@32e28000 { 75 compatible = "fsl,imx8mn-disp-blk-ctrl", "syscon"; 76 reg = <0x32e28000 0x100>; 77 power-domains = <&pgc_dispmix>, <&pgc_dispmix>, 78 <&pgc_dispmix>, <&pgc_mipi>, 79 <&pgc_mipi>; 80 power-domain-names = "bus", "isi", "lcdif", "mipi-dsi", 81 "mipi-csi"; 82 clocks = <&clk IMX8MN_CLK_DISP_AXI>, 83 <&clk IMX8MN_CLK_DISP_APB>, 84 <&clk IMX8MN_CLK_DISP_AXI_ROOT>, 85 <&clk IMX8MN_CLK_DISP_APB_ROOT>, 86 <&clk IMX8MN_CLK_DISP_AXI_ROOT>, 87 <&clk IMX8MN_CLK_DISP_APB_ROOT>, 88 <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>, 89 <&clk IMX8MN_CLK_DSI_CORE>, 90 <&clk IMX8MN_CLK_DSI_PHY_REF>, 91 <&clk IMX8MN_CLK_CSI1_PHY_REF>, 92 <&clk IMX8MN_CLK_CAMERA_PIXEL_ROOT>; 93 clock-names = "disp_axi", "disp_apb", "disp_axi_root", "disp_apb_root", 94 "lcdif-axi", "lcdif-apb", "lcdif-pix", "dsi-pclk", 95 "dsi-ref", "csi-aclk", "csi-pclk"; 96 #power-domain-cells = <1>; 97 };