cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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fsl,imx8mp-hsio-blk-ctrl.yaml (1832B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: NXP i.MX8MP HSIO blk-ctrl
      8
      9maintainers:
     10  - Lucas Stach <l.stach@pengutronix.de>
     11
     12description:
     13  The i.MX8MP HSIO blk-ctrl is a top-level peripheral providing access to
     14  the NoC and ensuring proper power sequencing of the high-speed IO
     15  (USB an PCIe) peripherals located in the HSIO domain of the SoC.
     16
     17properties:
     18  compatible:
     19    items:
     20      - const: fsl,imx8mp-hsio-blk-ctrl
     21      - const: syscon
     22
     23  reg:
     24    maxItems: 1
     25
     26  '#power-domain-cells':
     27    const: 1
     28
     29  power-domains:
     30    minItems: 6
     31    maxItems: 6
     32
     33  power-domain-names:
     34    items:
     35      - const: bus
     36      - const: usb
     37      - const: usb-phy1
     38      - const: usb-phy2
     39      - const: pcie
     40      - const: pcie-phy
     41
     42  clocks:
     43    minItems: 2
     44    maxItems: 2
     45
     46  clock-names:
     47    items:
     48      - const: usb
     49      - const: pcie
     50
     51required:
     52  - compatible
     53  - reg
     54  - power-domains
     55  - power-domain-names
     56  - clocks
     57  - clock-names
     58
     59additionalProperties: false
     60
     61examples:
     62  - |
     63    #include <dt-bindings/clock/imx8mp-clock.h>
     64    #include <dt-bindings/power/imx8mp-power.h>
     65
     66    hsio_blk_ctrl: blk-ctrl@32f10000 {
     67        compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon";
     68        reg = <0x32f10000 0x24>;
     69        clocks = <&clk IMX8MP_CLK_USB_ROOT>,
     70                 <&clk IMX8MP_CLK_PCIE_ROOT>;
     71        clock-names = "usb", "pcie";
     72        power-domains = <&pgc_hsiomix>, <&pgc_hsiomix>,
     73                        <&pgc_usb1_phy>, <&pgc_usb2_phy>,
     74                        <&pgc_hsiomix>, <&pgc_pcie_phy>;
     75        power-domain-names = "bus", "usb", "usb-phy1",
     76                             "usb-phy2", "pcie", "pcie-phy";
     77        #power-domain-cells = <1>;
     78    };