cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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pwrap.txt (2709B)


      1MediaTek PMIC Wrapper Driver
      2
      3This document describes the binding for the MediaTek PMIC wrapper.
      4
      5On MediaTek SoCs the PMIC is connected via SPI. The SPI master interface
      6is not directly visible to the CPU, but only through the PMIC wrapper
      7inside the SoC. The communication between the SoC and the PMIC can
      8optionally be encrypted. Also a non standard Dual IO SPI mode can be
      9used to increase speed.
     10
     11IP Pairing
     12
     13on MT8135 the pins of some SoC internal peripherals can be on the PMIC.
     14The signals of these pins are routed over the SPI bus using the pwrap
     15bridge. In the binding description below the properties needed for bridging
     16are marked with "IP Pairing". These are optional on SoCs which do not support
     17IP Pairing
     18
     19Required properties in pwrap device node.
     20- compatible:
     21	"mediatek,mt2701-pwrap" for MT2701/7623 SoCs
     22	"mediatek,mt6765-pwrap" for MT6765 SoCs
     23	"mediatek,mt6779-pwrap" for MT6779 SoCs
     24	"mediatek,mt6797-pwrap" for MT6797 SoCs
     25	"mediatek,mt6873-pwrap" for MT6873/8192 SoCs
     26	"mediatek,mt7622-pwrap" for MT7622 SoCs
     27	"mediatek,mt8135-pwrap" for MT8135 SoCs
     28	"mediatek,mt8173-pwrap" for MT8173 SoCs
     29	"mediatek,mt8183-pwrap" for MT8183 SoCs
     30	"mediatek,mt8186-pwrap" for MT8186 SoCs
     31	"mediatek,mt8195-pwrap" for MT8195 SoCs
     32	"mediatek,mt8516-pwrap" for MT8516 SoCs
     33- interrupts: IRQ for pwrap in SOC
     34- reg-names: "pwrap" is required; "pwrap-bridge" is optional.
     35  "pwrap": Main registers base
     36  "pwrap-bridge": bridge base (IP Pairing)
     37- reg: Must contain an entry for each entry in reg-names.
     38- clock-names: Must include the following entries:
     39  "spi": SPI bus clock
     40  "wrap": Main module clock
     41- clocks: Must contain an entry for each entry in clock-names.
     42
     43Optional properities:
     44- reset-names: Some SoCs include the following entries:
     45  "pwrap"
     46  "pwrap-bridge" (IP Pairing)
     47- resets: Must contain an entry for each entry in reset-names.
     48- pmic: Using either MediaTek PMIC MFD as the child device of pwrap
     49  See the following for child node definitions:
     50  Documentation/devicetree/bindings/mfd/mt6397.txt
     51  or the regulator-only device as the child device of pwrap, such as MT6380.
     52  See the following definitions for such kinds of devices.
     53  Documentation/devicetree/bindings/regulator/mt6380-regulator.txt
     54
     55Example:
     56	pwrap: pwrap@1000f000 {
     57		compatible = "mediatek,mt8135-pwrap";
     58		reg = <0 0x1000f000 0 0x1000>,
     59			<0 0x11017000 0 0x1000>;
     60		reg-names = "pwrap", "pwrap-bridge";
     61		interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
     62		resets = <&infracfg MT8135_INFRA_PMIC_WRAP_RST>,
     63				<&pericfg MT8135_PERI_PWRAP_BRIDGE_SW_RST>;
     64		reset-names = "pwrap", "pwrap-bridge";
     65		clocks = <&clk26m>, <&clk26m>;
     66		clock-names = "spi", "wrap";
     67
     68		pmic {
     69			compatible = "mediatek,mt6397";
     70		};
     71	};