cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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qcom,aoss-qmp.yaml (2816B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/soc/qcom/qcom,aoss-qmp.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Qualcomm Always-On Subsystem side channel binding
      8
      9maintainers:
     10  - Bjorn Andersson <bjorn.andersson@linaro.org>
     11
     12description:
     13  This binding describes the hardware component responsible for side channel
     14  requests to the always-on subsystem (AOSS), used for certain power management
     15  requests that is not handled by the standard RPMh interface. Each client in the
     16  SoC has it's own block of message RAM and IRQ for communication with the AOSS.
     17  The protocol used to communicate in the message RAM is known as Qualcomm
     18  Messaging Protocol (QMP)
     19
     20  The AOSS side channel exposes control over a set of resources, used to control
     21  a set of debug related clocks and to affect the low power state of resources
     22  related to the secondary subsystems.
     23
     24properties:
     25  compatible:
     26    items:
     27      - enum:
     28          - qcom,sc7180-aoss-qmp
     29          - qcom,sc7280-aoss-qmp
     30          - qcom,sc8180x-aoss-qmp
     31          - qcom,sdm845-aoss-qmp
     32          - qcom,sm6350-aoss-qmp
     33          - qcom,sm8150-aoss-qmp
     34          - qcom,sm8250-aoss-qmp
     35          - qcom,sm8350-aoss-qmp
     36      - const: qcom,aoss-qmp
     37
     38  reg:
     39    maxItems: 1
     40    description:
     41      The base address and size of the message RAM for this client's
     42      communication with the AOSS
     43
     44  interrupts:
     45    maxItems: 1
     46    description:
     47      Should specify the AOSS message IRQ for this client
     48
     49  mboxes:
     50    maxItems: 1
     51    description:
     52      Reference to the mailbox representing the outgoing doorbell in APCS for
     53      this client, as described in mailbox/mailbox.txt
     54
     55  "#clock-cells":
     56    const: 0
     57    description:
     58      The single clock represents the QDSS clock.
     59
     60required:
     61  - compatible
     62  - reg
     63  - interrupts
     64  - mboxes
     65  - "#clock-cells"
     66
     67additionalProperties: false
     68
     69patternProperties:
     70  "^(cx|mx|ebi)$":
     71    type: object
     72    description:
     73      The AOSS side channel also provides the controls for three cooling devices,
     74      these are expressed as subnodes of the QMP node. The name of the node is
     75      used to identify the resource and must therefor be "cx", "mx" or "ebi".
     76
     77    properties:
     78      "#cooling-cells":
     79        const: 2
     80
     81    required:
     82      - "#cooling-cells"
     83
     84    additionalProperties: false
     85
     86examples:
     87  - |
     88    #include <dt-bindings/interrupt-controller/arm-gic.h>
     89
     90    aoss_qmp: qmp@c300000 {
     91      compatible = "qcom,sdm845-aoss-qmp", "qcom,aoss-qmp";
     92      reg = <0x0c300000 0x100000>;
     93      interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
     94      mboxes = <&apss_shared 0>;
     95
     96      #clock-cells = <0>;
     97
     98      cx_cdev: cx {
     99        #cooling-cells = <2>;
    100      };
    101
    102      mx_cdev: mx {
    103        #cooling-cells = <2>;
    104      };
    105    };
    106...