cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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exynos-usi.yaml (4432B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/soc/samsung/exynos-usi.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Samsung's Exynos USI (Universal Serial Interface) binding
      8
      9maintainers:
     10  - Sam Protsenko <semen.protsenko@linaro.org>
     11  - Krzysztof Kozlowski <krzk@kernel.org>
     12
     13description: |
     14  USI IP-core provides selectable serial protocol (UART, SPI or High-Speed I2C).
     15  USI shares almost all internal circuits within each protocol, so only one
     16  protocol can be chosen at a time. USI is modeled as a node with zero or more
     17  child nodes, each representing a serial sub-node device. The mode setting
     18  selects which particular function will be used.
     19
     20properties:
     21  $nodename:
     22    pattern: "^usi@[0-9a-f]+$"
     23
     24  compatible:
     25    enum:
     26      - samsung,exynos850-usi   # for USIv2 (Exynos850, ExynosAutoV9)
     27
     28  reg: true
     29
     30  clocks: true
     31
     32  clock-names: true
     33
     34  ranges: true
     35
     36  "#address-cells":
     37    const: 1
     38
     39  "#size-cells":
     40    const: 1
     41
     42  samsung,sysreg:
     43    $ref: /schemas/types.yaml#/definitions/phandle-array
     44    items:
     45      - items:
     46          - description: phandle to System Register syscon node
     47          - description: offset of SW_CONF register for this USI controller
     48    description:
     49      Should be phandle/offset pair. The phandle to System Register syscon node
     50      (for the same domain where this USI controller resides) and the offset
     51      of SW_CONF register for this USI controller.
     52
     53  samsung,mode:
     54    $ref: /schemas/types.yaml#/definitions/uint32
     55    description:
     56      Selects USI function (which serial protocol to use). Refer to
     57      <include/dt-bindings/soc/samsung,exynos-usi.h> for valid USI mode values.
     58
     59  samsung,clkreq-on:
     60    type: boolean
     61    description:
     62      Enable this property if underlying protocol requires the clock to be
     63      continuously provided without automatic gating. As suggested by SoC
     64      manual, it should be set in case of SPI/I2C slave, UART Rx and I2C
     65      multi-master mode. Usually this property is needed if USI mode is set
     66      to "UART".
     67
     68      This property is optional.
     69
     70patternProperties:
     71  "^i2c@[0-9a-f]+$":
     72    $ref: /schemas/i2c/i2c-exynos5.yaml
     73    description: Child node describing underlying I2C
     74
     75  "^serial@[0-9a-f]+$":
     76    $ref: /schemas/serial/samsung_uart.yaml
     77    description: Child node describing underlying UART/serial
     78
     79  "^spi@[0-9a-f]+$":
     80    $ref: /schemas/spi/samsung,spi.yaml
     81    description: Child node describing underlying SPI
     82
     83required:
     84  - compatible
     85  - ranges
     86  - "#address-cells"
     87  - "#size-cells"
     88  - samsung,sysreg
     89  - samsung,mode
     90
     91if:
     92  properties:
     93    compatible:
     94      contains:
     95        enum:
     96          - samsung,exynos850-usi
     97
     98then:
     99  properties:
    100    reg:
    101      maxItems: 1
    102
    103    clocks:
    104      items:
    105        - description: Bus (APB) clock
    106        - description: Operating clock for UART/SPI/I2C protocol
    107
    108    clock-names:
    109      items:
    110        - const: pclk
    111        - const: ipclk
    112
    113  required:
    114    - reg
    115    - clocks
    116    - clock-names
    117
    118else:
    119  properties:
    120    reg: false
    121    clocks: false
    122    clock-names: false
    123    samsung,clkreq-on: false
    124
    125additionalProperties: false
    126
    127examples:
    128  - |
    129    #include <dt-bindings/interrupt-controller/arm-gic.h>
    130    #include <dt-bindings/soc/samsung,exynos-usi.h>
    131
    132    usi0: usi@138200c0 {
    133        compatible = "samsung,exynos850-usi";
    134        reg = <0x138200c0 0x20>;
    135        samsung,sysreg = <&sysreg_peri 0x1010>;
    136        samsung,mode = <USI_V2_UART>;
    137        samsung,clkreq-on; /* needed for UART mode */
    138        #address-cells = <1>;
    139        #size-cells = <1>;
    140        ranges;
    141        clocks = <&cmu_peri 32>, <&cmu_peri 31>;
    142        clock-names = "pclk", "ipclk";
    143
    144        serial_0: serial@13820000 {
    145            compatible = "samsung,exynos850-uart";
    146            reg = <0x13820000 0xc0>;
    147            interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
    148            clocks = <&cmu_peri 32>, <&cmu_peri 31>;
    149            clock-names = "uart", "clk_uart_baud0";
    150            status = "disabled";
    151        };
    152
    153        hsi2c_0: i2c@13820000 {
    154            compatible = "samsung,exynosautov9-hsi2c";
    155            reg = <0x13820000 0xc0>;
    156            interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
    157            #address-cells = <1>;
    158            #size-cells = <0>;
    159            clocks = <&cmu_peri 31>, <&cmu_peri 32>;
    160            clock-names = "hsi2c", "hsi2c_pclk";
    161            status = "disabled";
    162        };
    163    };