cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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cirrus,cs42l51.yaml (1436B)


      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/sound/cirrus,cs42l51.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: CS42L51 audio codec DT bindings
      8
      9maintainers:
     10  - Olivier Moysan <olivier.moysan@foss.st.com>
     11
     12properties:
     13  compatible:
     14    const: cirrus,cs42l51
     15
     16  reg:
     17    maxItems: 1
     18
     19  "#sound-dai-cells":
     20    const: 0
     21
     22  clocks:
     23    maxItems: 1
     24
     25  clock-names:
     26    items:
     27      - const: MCLK
     28
     29  reset-gpios:
     30    maxItems: 1
     31
     32  VL-supply:
     33    description: phandle to voltage regulator of digital interface section
     34
     35  VD-supply:
     36    description: phandle to voltage regulator of digital internal section
     37
     38  VA-supply:
     39    description: phandle to voltage regulator of analog internal section
     40
     41  VAHP-supply:
     42    description: phandle to voltage regulator of headphone
     43
     44required:
     45  - compatible
     46  - reg
     47  - "#sound-dai-cells"
     48
     49additionalProperties: false
     50
     51examples:
     52  - |
     53    #include <dt-bindings/gpio/gpio.h>
     54    i2c {
     55      #address-cells = <1>;
     56      #size-cells = <0>;
     57
     58      cs42l51@4a {
     59        compatible = "cirrus,cs42l51";
     60        reg = <0x4a>;
     61        #sound-dai-cells = <0>;
     62        clocks = <&mclk_prov>;
     63        clock-names = "MCLK";
     64        VL-supply = <&reg_audio>;
     65        VD-supply = <&reg_audio>;
     66        VA-supply = <&reg_audio>;
     67        VAHP-supply = <&reg_audio>;
     68        reset-gpios = <&gpiog 9 GPIO_ACTIVE_LOW>;
     69      };
     70    };
     71...