cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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fsl-sai.txt (3136B)

      1Freescale Synchronous Audio Interface (SAI).
      2
      3The SAI is based on I2S module that used communicating with audio codecs,
      4which provides a synchronous audio interface that supports fullduplex
      5serial interfaces with frame synchronization such as I2S, AC97, TDM, and
      6codec/DSP interfaces.
      7
      8Required properties:
      9
     10  - compatible		: Compatible list, contains "fsl,vf610-sai",
     11			  "fsl,imx6sx-sai", "fsl,imx6ul-sai",
     12			  "fsl,imx7ulp-sai", "fsl,imx8mq-sai",
     13			  "fsl,imx8qm-sai", "fsl,imx8mm-sai",
     14			  "fsl,imx8mn-sai", "fsl,imx8mp-sai", or
     15			  "fsl,imx8ulp-sai".
     16
     17  - reg			: Offset and length of the register set for the device.
     18
     19  - clocks		: Must contain an entry for each entry in clock-names.
     20
     21  - clock-names		: Must include the "bus" for register access and
     22			  "mclk1", "mclk2", "mclk3" for bit clock and frame
     23			  clock providing.
     24  - dmas		: Generic dma devicetree binding as described in
     25			  Documentation/devicetree/bindings/dma/dma.txt.
     26
     27  - dma-names		: Two dmas have to be defined, "tx" and "rx".
     28
     29  - pinctrl-names	: Must contain a "default" entry.
     30
     31  - pinctrl-NNN		: One property must exist for each entry in
     32			  pinctrl-names. See ../pinctrl/pinctrl-bindings.txt
     33			  for details of the property values.
     34
     35  - lsb-first		: Configures whether the LSB or the MSB is transmitted
     36			  first for the fifo data. If this property is absent,
     37			  the MSB is transmitted first as default, or the LSB
     38			  is transmitted first.
     39
     40  - fsl,sai-synchronous-rx: This is a boolean property. If present, indicating
     41			  that SAI will work in the synchronous mode (sync Tx
     42			  with Rx) which means both the transmitter and the
     43			  receiver will send and receive data by following
     44			  receiver's bit clocks and frame sync clocks.
     45
     46  - fsl,sai-asynchronous: This is a boolean property. If present, indicating
     47			  that SAI will work in the asynchronous mode, which
     48			  means both transmitter and receiver will send and
     49			  receive data by following their own bit clocks and
     50			  frame sync clocks separately.
     51
     52Optional properties:
     53
     54  - big-endian		: Boolean property, required if all the SAI
     55			  registers are big-endian rather than little-endian.
     56
     57Optional properties (for mx6ul):
     58
     59  - fsl,sai-mclk-direction-output: This is a boolean property. If present,
     60			 indicates that SAI will output the SAI MCLK clock.
     61
     62Note:
     63- If both fsl,sai-asynchronous and fsl,sai-synchronous-rx are absent, the
     64  default synchronous mode (sync Rx with Tx) will be used, which means both
     65  transmitter and receiver will send and receive data by following clocks
     66  of transmitter.
     67- fsl,sai-asynchronous and fsl,sai-synchronous-rx are exclusive.
     68
     69Example:
     70sai2: sai@40031000 {
     71	      compatible = "fsl,vf610-sai";
     72	      reg = <0x40031000 0x1000>;
     73	      pinctrl-names = "default";
     74	      pinctrl-0 = <&pinctrl_sai2_1>;
     75	      clocks = <&clks VF610_CLK_PLATFORM_BUS>,
     76		     <&clks VF610_CLK_SAI2>,
     77		     <&clks 0>, <&clks 0>;
     78	      clock-names = "bus", "mclk1", "mclk2", "mclk3";
     79	      dma-names = "tx", "rx";
     80	      dmas = <&edma0 0 VF610_EDMA_MUXID0_SAI2_TX>,
     81		   <&edma0 0 VF610_EDMA_MUXID0_SAI2_RX>;
     82	      big-endian;
     83	      lsb-first;
     84};