cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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mt2701-afe-pcm.txt (4384B)

      1Mediatek AFE PCM controller for mt2701
      2
      3Required properties:
      4- compatible: should be one of the followings.
      5	      - "mediatek,mt2701-audio"
      6	      - "mediatek,mt7622-audio"
      7- interrupts: should contain AFE and ASYS interrupts
      8- interrupt-names: should be "afe" and "asys"
      9- power-domains: should define the power domain
     10- clocks: Must contain an entry for each entry in clock-names
     11  See ../clocks/clock-bindings.txt for details
     12- clock-names: should have these clock names:
     13		"infra_sys_audio_clk",
     14		"top_audio_mux1_sel",
     15		"top_audio_mux2_sel",
     16		"top_audio_a1sys_hp",
     17		"top_audio_a2sys_hp",
     18		"i2s0_src_sel",
     19		"i2s1_src_sel",
     20		"i2s2_src_sel",
     21		"i2s3_src_sel",
     22		"i2s0_src_div",
     23		"i2s1_src_div",
     24		"i2s2_src_div",
     25		"i2s3_src_div",
     26		"i2s0_mclk_en",
     27		"i2s1_mclk_en",
     28		"i2s2_mclk_en",
     29		"i2s3_mclk_en",
     30		"i2so0_hop_ck",
     31		"i2so1_hop_ck",
     32		"i2so2_hop_ck",
     33		"i2so3_hop_ck",
     34		"i2si0_hop_ck",
     35		"i2si1_hop_ck",
     36		"i2si2_hop_ck",
     37		"i2si3_hop_ck",
     38		"asrc0_out_ck",
     39		"asrc1_out_ck",
     40		"asrc2_out_ck",
     41		"asrc3_out_ck",
     42		"audio_afe_pd",
     43		"audio_afe_conn_pd",
     44		"audio_a1sys_pd",
     45		"audio_a2sys_pd",
     46		"audio_mrgif_pd";
     47- assigned-clocks: list of input clocks and dividers for the audio system.
     48		   See ../clocks/clock-bindings.txt for details.
     49- assigned-clocks-parents: parent of input clocks of assigned clocks.
     50- assigned-clock-rates: list of clock frequencies of assigned clocks.
     51
     52Must be a subnode of MediaTek audsys device tree node.
     53See ../arm/mediatek/mediatek,audsys.txt for details about the parent node.
     54
     55Example:
     56
     57	audsys: audio-subsystem@11220000 {
     58		compatible = "mediatek,mt2701-audsys", "syscon";
     59		...
     60
     61		afe: audio-controller {
     62			compatible = "mediatek,mt2701-audio";
     63			interrupts =  <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
     64				      <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
     65			interrupt-names	= "afe", "asys";
     66			power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
     67
     68			clocks = <&infracfg CLK_INFRA_AUDIO>,
     69				 <&topckgen CLK_TOP_AUD_MUX1_SEL>,
     70				 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
     71				 <&topckgen CLK_TOP_AUD_48K_TIMING>,
     72				 <&topckgen CLK_TOP_AUD_44K_TIMING>,
     73				 <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
     74				 <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
     75				 <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
     76				 <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
     77				 <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
     78				 <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
     79				 <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
     80				 <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
     81				 <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
     82				 <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
     83				 <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
     84				 <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
     85				 <&audsys CLK_AUD_I2SO1>,
     86				 <&audsys CLK_AUD_I2SO2>,
     87				 <&audsys CLK_AUD_I2SO3>,
     88				 <&audsys CLK_AUD_I2SO4>,
     89				 <&audsys CLK_AUD_I2SIN1>,
     90				 <&audsys CLK_AUD_I2SIN2>,
     91				 <&audsys CLK_AUD_I2SIN3>,
     92				 <&audsys CLK_AUD_I2SIN4>,
     93				 <&audsys CLK_AUD_ASRCO1>,
     94				 <&audsys CLK_AUD_ASRCO2>,
     95				 <&audsys CLK_AUD_ASRCO3>,
     96				 <&audsys CLK_AUD_ASRCO4>,
     97				 <&audsys CLK_AUD_AFE>,
     98				 <&audsys CLK_AUD_AFE_CONN>,
     99				 <&audsys CLK_AUD_A1SYS>,
    100				 <&audsys CLK_AUD_A2SYS>,
    101				 <&audsys CLK_AUD_AFE_MRGIF>;
    102
    103			clock-names = "infra_sys_audio_clk",
    104				      "top_audio_mux1_sel",
    105				      "top_audio_mux2_sel",
    106				      "top_audio_a1sys_hp",
    107				      "top_audio_a2sys_hp",
    108				      "i2s0_src_sel",
    109				      "i2s1_src_sel",
    110				      "i2s2_src_sel",
    111				      "i2s3_src_sel",
    112				      "i2s0_src_div",
    113				      "i2s1_src_div",
    114				      "i2s2_src_div",
    115				      "i2s3_src_div",
    116				      "i2s0_mclk_en",
    117				      "i2s1_mclk_en",
    118				      "i2s2_mclk_en",
    119				      "i2s3_mclk_en",
    120				      "i2so0_hop_ck",
    121				      "i2so1_hop_ck",
    122				      "i2so2_hop_ck",
    123				      "i2so3_hop_ck",
    124				      "i2si0_hop_ck",
    125				      "i2si1_hop_ck",
    126				      "i2si2_hop_ck",
    127				      "i2si3_hop_ck",
    128				      "asrc0_out_ck",
    129				      "asrc1_out_ck",
    130				      "asrc2_out_ck",
    131				      "asrc3_out_ck",
    132				      "audio_afe_pd",
    133				      "audio_afe_conn_pd",
    134				      "audio_a1sys_pd",
    135				      "audio_a2sys_pd",
    136				      "audio_mrgif_pd";
    137
    138			assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
    139					  <&topckgen CLK_TOP_AUD_MUX2_SEL>,
    140					  <&topckgen CLK_TOP_AUD_MUX1_DIV>,
    141					  <&topckgen CLK_TOP_AUD_MUX2_DIV>;
    142			assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
    143						 <&topckgen CLK_TOP_AUD2PLL_90M>;
    144			assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
    145		};
    146	};