cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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nvidia,tegra20-i2s.yaml (1564B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/sound/nvidia,tegra20-i2s.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: NVIDIA Tegra20 I2S Controller
      8
      9description: |
     10  The I2S Controller streams synchronous serial audio data between system
     11  memory and an external audio device. The controller supports the I2S Left
     12  Justified Mode, Right Justified Mode, and DSP mode formats.
     13
     14maintainers:
     15  - Thierry Reding <treding@nvidia.com>
     16  - Jon Hunter <jonathanh@nvidia.com>
     17
     18properties:
     19  compatible:
     20    const: nvidia,tegra20-i2s
     21
     22  reg:
     23    maxItems: 1
     24
     25  resets:
     26    maxItems: 1
     27
     28  reset-names:
     29    const: i2s
     30
     31  interrupts:
     32    maxItems: 1
     33
     34  clocks:
     35    minItems: 1
     36
     37  dmas:
     38    minItems: 2
     39
     40  dma-names:
     41    items:
     42      - const: rx
     43      - const: tx
     44
     45  nvidia,fixed-parent-rate:
     46    description: |
     47      Specifies whether board prefers parent clock to stay at a fixed rate.
     48      This allows multiple Tegra20 audio components work simultaneously by
     49      limiting number of supportable audio rates.
     50    type: boolean
     51
     52required:
     53  - compatible
     54  - reg
     55  - resets
     56  - reset-names
     57  - interrupts
     58  - clocks
     59  - dmas
     60  - dma-names
     61
     62additionalProperties: false
     63
     64examples:
     65  - |
     66    i2s@70002800 {
     67        compatible = "nvidia,tegra20-i2s";
     68        reg = <0x70002800 0x200>;
     69        interrupts = <45>;
     70        clocks = <&tegra_car 11>;
     71        resets = <&tegra_car 11>;
     72        reset-names = "i2s";
     73        dmas = <&apbdma 21>, <&apbdma 21>;
     74        dma-names = "rx", "tx";
     75    };
     76
     77...