cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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nvidia,tegra210-ahub.yaml (4924B)


      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/sound/nvidia,tegra210-ahub.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Tegra210 AHUB Device Tree Bindings
      8
      9description: |
     10  The Audio Hub (AHUB) comprises a collection of hardware accelerators
     11  for audio pre-processing, post-processing and a programmable full
     12  crossbar for routing audio data across these accelerators. It has
     13  external interfaces such as I2S, DMIC, DSPK. It interfaces with ADMA
     14  engine through ADMAIF.
     15
     16maintainers:
     17  - Jon Hunter <jonathanh@nvidia.com>
     18  - Sameer Pujar <spujar@nvidia.com>
     19
     20properties:
     21  $nodename:
     22    pattern: "^ahub@[0-9a-f]*$"
     23
     24  compatible:
     25    oneOf:
     26      - enum:
     27          - nvidia,tegra210-ahub
     28          - nvidia,tegra186-ahub
     29          - nvidia,tegra234-ahub
     30      - items:
     31          - const: nvidia,tegra194-ahub
     32          - const: nvidia,tegra186-ahub
     33
     34  reg:
     35    maxItems: 1
     36
     37  clocks:
     38    maxItems: 1
     39
     40  clock-names:
     41    const: ahub
     42
     43  assigned-clocks:
     44    maxItems: 1
     45
     46  assigned-clock-parents:
     47    maxItems: 1
     48
     49  assigned-clock-rates:
     50    maxItems: 1
     51
     52  "#address-cells":
     53    const: 1
     54
     55  "#size-cells":
     56    const: 1
     57
     58  ranges: true
     59
     60  ports:
     61    $ref: /schemas/graph.yaml#/properties/ports
     62    description: |
     63      Contains list of ACIF (Audio CIF) port nodes for AHUB (Audio Hub).
     64      These are connected to ACIF interfaces of AHUB clients. Thus the
     65      number of port nodes depend on the number of clients that AHUB may
     66      have depending on the SoC revision.
     67
     68    patternProperties:
     69      '^port@[0-9]':
     70        $ref: audio-graph-port.yaml#
     71        unevaluatedProperties: false
     72
     73patternProperties:
     74  '^i2s@[0-9a-f]+$':
     75    type: object
     76
     77  '^dmic@[0-9a-f]+$':
     78    type: object
     79    $ref: nvidia,tegra210-dmic.yaml#
     80
     81  '^admaif@[0-9a-f]+$':
     82    type: object
     83    $ref: nvidia,tegra210-admaif.yaml#
     84
     85  '^dspk@[0-9a-f]+$':
     86    type: object
     87    $ref: nvidia,tegra186-dspk.yaml#
     88
     89  '^mvc@[0-9a-f]+$':
     90    type: object
     91    $ref: nvidia,tegra210-mvc.yaml#
     92
     93  '^sfc@[0-9a-f]+$':
     94    type: object
     95    $ref: nvidia,tegra210-sfc.yaml#
     96
     97  '^amx@[0-9a-f]+$':
     98    type: object
     99    $ref: nvidia,tegra210-amx.yaml#
    100
    101  '^adx@[0-9a-f]+$':
    102    type: object
    103    $ref: nvidia,tegra210-adx.yaml#
    104
    105  '^amixer@[0-9a-f]+$':
    106    type: object
    107    $ref: nvidia,tegra210-mixer.yaml#
    108
    109  '^asrc@[0-9a-f]+$':
    110    type: object
    111    $ref: nvidia,tegra186-asrc.yaml#
    112
    113required:
    114  - compatible
    115  - reg
    116  - clocks
    117  - clock-names
    118  - assigned-clocks
    119  - assigned-clock-parents
    120  - "#address-cells"
    121  - "#size-cells"
    122  - ranges
    123
    124additionalProperties: false
    125
    126examples:
    127  - |
    128    #include<dt-bindings/clock/tegra210-car.h>
    129
    130    ahub@702d0800 {
    131        compatible = "nvidia,tegra210-ahub";
    132        reg = <0x702d0800 0x800>;
    133        clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
    134        clock-names = "ahub";
    135        assigned-clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
    136        assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
    137        #address-cells = <1>;
    138        #size-cells = <1>;
    139        ranges = <0x702d0000 0x702d0000 0x0000e400>;
    140
    141        // All AHUB child nodes below
    142        admaif@702d0000 {
    143            compatible = "nvidia,tegra210-admaif";
    144            reg = <0x702d0000 0x800>;
    145            dmas = <&adma 1>,  <&adma 1>,
    146               <&adma 2>,  <&adma 2>,
    147               <&adma 3>,  <&adma 3>,
    148               <&adma 4>,  <&adma 4>,
    149               <&adma 5>,  <&adma 5>,
    150               <&adma 6>,  <&adma 6>,
    151               <&adma 7>,  <&adma 7>,
    152               <&adma 8>,  <&adma 8>,
    153               <&adma 9>,  <&adma 9>,
    154               <&adma 10>, <&adma 10>;
    155            dma-names = "rx1",  "tx1",
    156                    "rx2",  "tx2",
    157                    "rx3",  "tx3",
    158                    "rx4",  "tx4",
    159                    "rx5",  "tx5",
    160                    "rx6",  "tx6",
    161                    "rx7",  "tx7",
    162                    "rx8",  "tx8",
    163                    "rx9",  "tx9",
    164                    "rx10", "tx10";
    165        };
    166
    167        i2s@702d1000 {
    168            compatible = "nvidia,tegra210-i2s";
    169            reg = <0x702d1000 0x100>;
    170            clocks = <&tegra_car TEGRA210_CLK_I2S0>;
    171            clock-names = "i2s";
    172            assigned-clocks = <&tegra_car TEGRA210_CLK_I2S0>;
    173            assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
    174            assigned-clock-rates = <1536000>;
    175            sound-name-prefix = "I2S1";
    176        };
    177
    178        dmic@702d4000 {
    179            compatible = "nvidia,tegra210-dmic";
    180            reg = <0x702d4000 0x100>;
    181            clocks = <&tegra_car TEGRA210_CLK_DMIC1>;
    182            clock-names = "dmic";
    183            assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC1>;
    184            assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
    185            assigned-clock-rates = <3072000>;
    186            sound-name-prefix = "DMIC1";
    187        };
    188
    189        // More child nodes to follow
    190    };
    191
    192...