cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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nvidia,tegra30-ahub.txt (2952B)

      1NVIDIA Tegra30 AHUB (Audio Hub)
      2
      3Required properties:
      4- compatible : For Tegra30, must contain "nvidia,tegra30-ahub".  For Tegra114,
      5  must contain "nvidia,tegra114-ahub".  For Tegra124, must contain
      6  "nvidia,tegra124-ahub".  Otherwise, must contain "nvidia,<chip>-ahub",
      7  plus at least one of the above, where <chip> is tegra132.
      8- reg : Should contain the register physical address and length for each of
      9  the AHUB's register blocks.
     10  - Tegra30 requires 2 entries, for the APBIF and AHUB/AUDIO register blocks.
     11  - Tegra114 requires an additional entry, for the APBIF2 register block.
     12- interrupts : Should contain AHUB interrupt
     13- clocks : Must contain an entry for each entry in clock-names.
     14  See ../clocks/clock-bindings.txt for details.
     15- clock-names : Must include the following entries:
     16  - d_audio
     17  - apbif
     18- resets : Must contain an entry for each entry in reset-names.
     19  See ../reset/reset.txt for details.
     20- reset-names : Must include the following entries:
     21  Tegra30 and later:
     22  - d_audio
     23  - apbif
     24  - i2s0
     25  - i2s1
     26  - i2s2
     27  - i2s3
     28  - i2s4
     29  - dam0
     30  - dam1
     31  - dam2
     32  - spdif
     33  Tegra114 and later additionally require:
     34  - amx
     35  - adx
     36  Tegra124 and later additionally require:
     37  - amx1
     38  - adx1
     39  - afc0
     40  - afc1
     41  - afc2
     42  - afc3
     43  - afc4
     44  - afc5
     45- ranges : The bus address mapping for the configlink register bus.
     46  Can be empty since the mapping is 1:1.
     47- dmas : Must contain an entry for each entry in clock-names.
     48  See ../dma/dma.txt for details.
     49- dma-names : Must include the following entries:
     50  - rx0 .. rx<n>
     51  - tx0 .. tx<n>
     52  ... where n is:
     53  Tegra30: 3
     54  Tegra114, Tegra124: 9
     55- #address-cells : For the configlink bus. Should be <1>;
     56- #size-cells : For the configlink bus. Should be <1>.
     57
     58AHUB client modules need to specify the IDs of their CIFs (Client InterFaces).
     59For RX CIFs, the numbers indicate the register number within AHUB routing
     60register space (APBIF 0..3 RX, I2S 0..5 RX, DAM 0..2 RX 0..1, SPDIF RX 0..1).
     61For TX CIFs, the numbers indicate the bit position within the AHUB routing
     62registers (APBIF 0..3 TX, I2S 0..5 TX, DAM 0..2 TX, SPDIF TX 0..1).
     63
     64Example:
     65
     66ahub@70080000 {
     67	compatible = "nvidia,tegra30-ahub";
     68	reg = <0x70080000 0x200 0x70080200 0x100>;
     69	interrupts = < 0 103 0x04 >;
     70	nvidia,dma-request-selector = <&apbdma 1>;
     71	clocks = <&tegra_car 106>, <&tegra_car 107>;
     72	clock-names = "d_audio", "apbif";
     73	resets = <&tegra_car 106>, <&tegra_car 107>, <&tegra_car 30>,
     74		<&tegra_car 11>, <&tegra_car 18>, <&tegra_car 101>,
     75		<&tegra_car 102>, <&tegra_car 108>, <&tegra_car 109>,
     76		<&tegra_car 110>, <&tegra_car 10>;
     77	reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
     78		"i2s3", "i2s4", "dam0", "dam1", "dam2",
     79		"spdif";
     80	dmas = <&apbdma 1>, <&apbdma 1>;
     81	       <&apbdma 2>, <&apbdma 2>;
     82	       <&apbdma 3>, <&apbdma 3>;
     83	       <&apbdma 4>, <&apbdma 4>;
     84	dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", "rx3", "tx3";
     85	ranges;
     86	#address-cells = <1>;
     87	#size-cells = <1>;
     88};