cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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omap-mcbsp.txt (1291B)


      1* Texas Instruments OMAP2+ McBSP module
      2
      3Required properties:
      4- compatible: "ti,omap2420-mcbsp" for McBSP on OMAP2420
      5	      "ti,omap2430-mcbsp" for McBSP on OMAP2430
      6	      "ti,omap3-mcbsp" for McBSP on OMAP3
      7	      "ti,omap4-mcbsp" for McBSP on OMAP4 and newer SoC
      8- reg: Register location and size, for OMAP4+ as an array:
      9       <MPU access base address, size>,
     10       <L3 interconnect address, size>;
     11- reg-names: Array of strings associated with the address space
     12- interrupts: Interrupt numbers for the McBSP port, as an array in case the
     13	      McBSP IP have more interrupt lines:
     14	<OCP compliant irq>,
     15	<TX irq>,
     16	<RX irq>;
     17- interrupt-names: Array of strings associated with the interrupt numbers
     18- ti,buffer-size: Size of the FIFO on the port (OMAP2430 and newer SoC)
     19- ti,hwmods: Name of the hwmod associated to the McBSP port
     20
     21Example:
     22
     23mcbsp2: mcbsp@49022000 {
     24	compatible = "ti,omap3-mcbsp";
     25	reg = <0x49022000 0xff>,
     26	      <0x49028000 0xff>;
     27	reg-names = "mpu", "sidetone";
     28	interrupts = <0 17 0x4>, /* OCP compliant interrupt */
     29		     <0 62 0x4>, /* TX interrupt */
     30		     <0 63 0x4>, /* RX interrupt */
     31		     <0 4 0x4>;  /* Sidetone */
     32	interrupt-names = "common", "tx", "rx", "sidetone";
     33	interrupt-parent = <&intc>;
     34	ti,buffer-size = <1280>;
     35	ti,hwmods = "mcbsp2";
     36};