cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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ti,tas5086.txt (1503B)


      1Texas Instruments TAS5086 6-channel PWM Processor
      2
      3Required properties:
      4
      5 - compatible:		Should contain "ti,tas5086".
      6 - reg:			The i2c address. Should contain <0x1b>.
      7
      8Optional properties:
      9
     10 - reset-gpio: 		A GPIO spec to define which pin is connected to the
     11			chip's !RESET pin. If specified, the driver will
     12			assert a hardware reset at probe time.
     13
     14 - ti,charge-period:	This property should contain the time in microseconds
     15			that closely matches the external single-ended
     16			split-capacitor charge period. The hardware chip
     17			waits for this period of time before starting the
     18			PWM signals. This helps reduce pops and clicks.
     19
     20			When not specified, the hardware default of 1300ms
     21			is retained.
     22
     23 - ti,mid-z-channel-X:	Boolean properties, X being a number from 1 to 6.
     24			If given, channel X will start with the Mid-Z start
     25			sequence, otherwise the default Low-Z scheme is used.
     26
     27			The correct configuration depends on how the power
     28			stages connected to the PWM output pins work. Not all
     29			power stages are compatible to Mid-Z - please refer
     30			to the datasheets for more details.
     31
     32			Most systems should not set any of these properties.
     33
     34 - avdd-supply:         Power supply for AVDD, providing 3.3V
     35 - dvdd-supply:         Power supply for DVDD, providing 3.3V
     36
     37Examples:
     38
     39	i2c_bus {
     40		tas5086@1b {
     41			compatible = "ti,tas5086";
     42			reg = <0x1b>;
     43			reset-gpio = <&gpio 23 0>;
     44			ti,charge-period = <156000>;
     45			avdd-supply = <&vdd_3v3_reg>;
     46			dvdd-supply = <&vdd_3v3_reg>;
     47		};
     48	};