wlf,wm8731.yaml (2153B)
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/sound/wlf,wm8731.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Wolfson Microelectromics WM8731 audio CODEC 8 9maintainers: 10 - patches@opensource.cirrus.com 11 12description: | 13 Wolfson Microelectronics WM8731 audio CODEC 14 15 Pins on the device (for linking into audio routes): 16 * LOUT: Left Channel Line Output 17 * ROUT: Right Channel Line Output 18 * LHPOUT: Left Channel Headphone Output 19 * RHPOUT: Right Channel Headphone Output 20 * LLINEIN: Left Channel Line Input 21 * RLINEIN: Right Channel Line Input 22 * MICIN: Microphone Input 23 24properties: 25 compatible: 26 enum: 27 - wlf,wm8731 28 29 reg: 30 maxItems: 1 31 32 "#sound-dai-cells": 33 const: 0 34 35 clocks: 36 description: Clock provider for MCLK pin. 37 maxItems: 1 38 39 clock-names: 40 items: 41 - const: mclk 42 43 AVDD-supply: 44 description: Analog power supply regulator on the AVDD pin. 45 46 HPVDD-supply: 47 description: Headphone power supply regulator on the HPVDD pin. 48 49 DBVDD-supply: 50 description: Digital buffer supply regulator for the DBVDD pin. 51 52 DCVDD-supply: 53 description: Digital core supply regulator for the DCVDD pin. 54 55 spi-max-frequency: true 56 57additionalProperties: false 58 59required: 60 - reg 61 - compatible 62 - AVDD-supply 63 - HPVDD-supply 64 - DBVDD-supply 65 - DCVDD-supply 66 67examples: 68 - | 69 spi { 70 #address-cells = <1>; 71 #size-cells = <0>; 72 wm8731_i2c: codec@0 { 73 compatible = "wlf,wm8731"; 74 reg = <0>; 75 spi-max-frequency = <12500000>; 76 77 AVDD-supply = <&avdd_reg>; 78 HPVDD-supply = <&hpvdd_reg>; 79 DCVDD-supply = <&dcvdd_reg>; 80 DBVDD-supply = <&dbvdd_reg>; 81 }; 82 }; 83 - | 84 85 i2c { 86 #address-cells = <1>; 87 #size-cells = <0>; 88 wm8731_spi: codec@1b { 89 compatible = "wlf,wm8731"; 90 reg = <0x1b>; 91 92 AVDD-supply = <&avdd_reg>; 93 HPVDD-supply = <&hpvdd_reg>; 94 DCVDD-supply = <&dcvdd_reg>; 95 DBVDD-supply = <&dbvdd_reg>; 96 }; 97 };