cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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mediatek,spi-slave-mt27xx.yaml (1262B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/spi/mediatek,spi-slave-mt27xx.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: SPI Slave controller for MediaTek ARM SoCs
      8
      9maintainers:
     10  - Leilk Liu <leilk.liu@mediatek.com>
     11
     12allOf:
     13  - $ref: "/schemas/spi/spi-controller.yaml#"
     14
     15properties:
     16  compatible:
     17    enum:
     18      - mediatek,mt2712-spi-slave
     19      - mediatek,mt8195-spi-slave
     20
     21  reg:
     22    maxItems: 1
     23
     24  interrupts:
     25    maxItems: 1
     26
     27  clocks:
     28    maxItems: 1
     29
     30  clock-names:
     31    items:
     32      - const: spi
     33
     34required:
     35  - compatible
     36  - reg
     37  - interrupts
     38  - clocks
     39  - clock-names
     40
     41unevaluatedProperties: false
     42
     43examples:
     44  - |
     45    #include <dt-bindings/clock/mt2712-clk.h>
     46    #include <dt-bindings/gpio/gpio.h>
     47    #include <dt-bindings/interrupt-controller/arm-gic.h>
     48    #include <dt-bindings/interrupt-controller/irq.h>
     49
     50    spi@10013000 {
     51      compatible = "mediatek,mt2712-spi-slave";
     52      reg = <0x10013000 0x100>;
     53      interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_LOW>;
     54      clocks = <&infracfg CLK_INFRA_AO_SPI1>;
     55      clock-names = "spi";
     56      assigned-clocks = <&topckgen CLK_TOP_SPISLV_SEL>;
     57      assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
     58    };