cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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mxicy,mx25f0a-spi.yaml (1344B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/spi/mxicy,mx25f0a-spi.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Macronix SPI controller device tree bindings
      8
      9maintainers:
     10  - Miquel Raynal <miquel.raynal@bootlin.com>
     11
     12allOf:
     13  - $ref: "spi-controller.yaml#"
     14
     15properties:
     16  compatible:
     17    const: mxicy,mx25f0a-spi
     18
     19  reg:
     20    minItems: 2
     21    maxItems: 2
     22
     23  reg-names:
     24    items:
     25      - const: regs
     26      - const: dirmap
     27
     28  interrupts:
     29    maxItems: 1
     30
     31  clocks:
     32    minItems: 3
     33    maxItems: 3
     34
     35  clock-names:
     36    items:
     37      - const: send_clk
     38      - const: send_dly_clk
     39      - const: ps_clk
     40
     41  nand-ecc-engine:
     42    description: NAND ECC engine used by the SPI controller in order to perform
     43      on-the-fly correction when using a SPI-NAND memory.
     44    $ref: /schemas/types.yaml#/definitions/phandle
     45
     46required:
     47  - compatible
     48  - reg
     49  - reg-names
     50  - clocks
     51  - clock-names
     52
     53unevaluatedProperties: false
     54
     55examples:
     56  - |
     57    spi@43c30000 {
     58      compatible = "mxicy,mx25f0a-spi";
     59      reg = <0x43c30000 0x10000>, <0xa0000000 0x20000000>;
     60      reg-names = "regs", "dirmap";
     61      clocks = <&clkwizard 0>, <&clkwizard 1>, <&clkc 18>;
     62      clock-names = "send_clk", "send_dly_clk", "ps_clk";
     63      #address-cells = <1>;
     64      #size-cells = <0>;
     65    };