cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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nuvoton,npcm-pspi.txt (1326B)

      1Nuvoton NPCM Peripheral Serial Peripheral Interface(PSPI) controller driver
      2
      3Nuvoton NPCM7xx SOC support two PSPI channels.
      4
      5Required properties:
      6 - compatible : "nuvoton,npcm750-pspi" for NPCM7XX BMC
      7 - #address-cells : should be 1. see spi-bus.txt
      8 - #size-cells : should be 0. see spi-bus.txt
      9 - specifies physical base address and size of the register.
     10 - interrupts : contain PSPI interrupt.
     11 - clocks : phandle of PSPI reference clock.
     12 - clock-names: Should be "clk_apb5".
     13 - pinctrl-names : a pinctrl state named "default" must be defined.
     14 - pinctrl-0 : phandle referencing pin configuration of the device.
     15 - resets : phandle to the reset control for this device.
     16 - cs-gpios: Specifies the gpio pins to be used for chipselects.
     17            See: Documentation/devicetree/bindings/spi/spi-bus.txt
     18
     19Optional properties:
     20- clock-frequency : Input clock frequency to the PSPI block in Hz.
     21		    Default is 25000000 Hz.
     22
     23spi0: spi@f0200000 {
     24	compatible = "nuvoton,npcm750-pspi";
     25	reg = <0xf0200000 0x1000>;
     26	pinctrl-names = "default";
     27	pinctrl-0 = <&pspi1_pins>;
     28	#address-cells = <1>;
     29	#size-cells = <0>;
     30	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
     31	clocks = <&clk NPCM7XX_CLK_APB5>;
     32	clock-names = "clk_apb5";
     33	resets = <&rstc NPCM7XX_RESET_IPSRST2 NPCM7XX_RESET_PSPI1>
     34	cs-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
     35};