cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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nvidia,tegra114-spi.txt (2194B)


      1NVIDIA Tegra114 SPI controller.
      2
      3Required properties:
      4- compatible : For Tegra114, must contain "nvidia,tegra114-spi".
      5  Otherwise, must contain '"nvidia,<chip>-spi", "nvidia,tegra114-spi"' where
      6  <chip> is tegra124, tegra132, or tegra210.
      7- reg: Should contain SPI registers location and length.
      8- interrupts: Should contain SPI interrupts.
      9- clock-names : Must include the following entries:
     10  - spi
     11- resets : Must contain an entry for each entry in reset-names.
     12  See ../reset/reset.txt for details.
     13- reset-names : Must include the following entries:
     14  - spi
     15- dmas : Must contain an entry for each entry in clock-names.
     16  See ../dma/dma.txt for details.
     17- dma-names : Must include the following entries:
     18  - rx
     19  - tx
     20- clocks : Must contain an entry for each entry in clock-names.
     21  See ../clocks/clock-bindings.txt for details.
     22
     23Recommended properties:
     24- spi-max-frequency: Definition as per
     25                     Documentation/devicetree/bindings/spi/spi-bus.txt
     26Optional properties:
     27- nvidia,tx-clk-tap-delay: Delays the clock going out to the external device
     28  with this tap value. This property is used to tune the outgoing data from
     29  Tegra SPI master with respect to outgoing Tegra SPI master clock.
     30  Tap values vary based on the platform design trace lengths from Tegra SPI
     31  to corresponding slave devices. Valid tap values are from 0 thru 63.
     32- nvidia,rx-clk-tap-delay: Delays the clock coming in from the external device
     33  with this tap value. This property is used to adjust the Tegra SPI master
     34  clock with respect to the data from the SPI slave device.
     35  Tap values vary based on the platform design trace lengths from Tegra SPI
     36  to corresponding slave devices. Valid tap values are from 0 thru 63.
     37
     38Example:
     39
     40spi@7000d600 {
     41	compatible = "nvidia,tegra114-spi";
     42	reg = <0x7000d600 0x200>;
     43	interrupts = <0 82 0x04>;
     44	spi-max-frequency = <25000000>;
     45	#address-cells = <1>;
     46	#size-cells = <0>;
     47	clocks = <&tegra_car 44>;
     48	clock-names = "spi";
     49	resets = <&tegra_car 44>;
     50	reset-names = "spi";
     51	dmas = <&apbdma 16>, <&apbdma 16>;
     52	dma-names = "rx", "tx";
     53	<spi-client>@<bus_num> {
     54		...
     55		...
     56		nvidia,rx-clk-tap-delay = <0>;
     57		nvidia,tx-clk-tap-delay = <16>;
     58		...
     59	};
     60
     61};