cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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nvidia,tegra210-quad.yaml (2823B)

      1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/spi/nvidia,tegra210-quad.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Tegra Quad SPI Controller
      8
      9maintainers:
     10  - Thierry Reding <thierry.reding@gmail.com>
     11  - Jonathan Hunter <jonathanh@nvidia.com>
     12
     13allOf:
     14  - $ref: "spi-controller.yaml#"
     15
     16properties:
     17  compatible:
     18    enum:
     19      - nvidia,tegra210-qspi
     20      - nvidia,tegra186-qspi
     21      - nvidia,tegra194-qspi
     22      - nvidia,tegra234-qspi
     23
     24  reg:
     25    maxItems: 1
     26
     27  interrupts:
     28    maxItems: 1
     29
     30  clock-names:
     31    items:
     32      - const: qspi
     33      - const: qspi_out
     34
     35  clocks:
     36    maxItems: 2
     37
     38  resets:
     39    maxItems: 1
     40
     41  dmas:
     42    maxItems: 2
     43
     44  dma-names:
     45    items:
     46      - const: rx
     47      - const: tx
     48
     49patternProperties:
     50  "@[0-9a-f]+":
     51    type: object
     52
     53    properties:
     54      spi-rx-bus-width:
     55        enum: [1, 2, 4]
     56
     57      spi-tx-bus-width:
     58        enum: [1, 2, 4]
     59
     60      nvidia,tx-clk-tap-delay:
     61        description:
     62          Delays the clock going out to device with this tap value.
     63          Tap value varies based on platform design trace lengths from Tegra
     64          QSPI to corresponding slave device.
     65        $ref: /schemas/types.yaml#/definitions/uint32
     66        minimum: 0
     67        maximum: 31
     68
     69      nvidia,rx-clk-tap-delay:
     70        description:
     71          Delays the clock coming in from the device with this tap value.
     72          Tap value varies based on platform design trace lengths from Tegra
     73          QSPI to corresponding slave device.
     74        $ref: /schemas/types.yaml#/definitions/uint32
     75        minimum: 0
     76        maximum: 255
     77
     78    required:
     79      - reg
     80
     81required:
     82  - compatible
     83  - reg
     84  - interrupts
     85  - clock-names
     86  - clocks
     87  - resets
     88
     89unevaluatedProperties: false
     90
     91examples:
     92  - |
     93    #include <dt-bindings/clock/tegra210-car.h>
     94    #include <dt-bindings/reset/tegra210-car.h>
     95    #include <dt-bindings/interrupt-controller/arm-gic.h>
     96    spi@70410000 {
     97            compatible = "nvidia,tegra210-qspi";
     98            reg = <0x70410000 0x1000>;
     99            interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
    100            #address-cells = <1>;
    101            #size-cells = <0>;
    102            clocks = <&tegra_car TEGRA210_CLK_QSPI>,
    103                     <&tegra_car TEGRA210_CLK_QSPI_PM>;
    104            clock-names = "qspi", "qspi_out";
    105            resets = <&tegra_car 211>;
    106            dmas = <&apbdma 5>, <&apbdma 5>;
    107            dma-names = "rx", "tx";
    108
    109            flash@0 {
    110                    compatible = "jedec,spi-nor";
    111                    reg = <0>;
    112                    spi-max-frequency = <104000000>;
    113                    spi-tx-bus-width = <2>;
    114                    spi-rx-bus-width = <2>;
    115                    nvidia,tx-clk-tap-delay = <0>;
    116                    nvidia,rx-clk-tap-delay = <0>;
    117            };
    118    };