cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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omap-spi.yaml (2756B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/spi/omap-spi.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: SPI controller bindings for OMAP and K3 SoCs
      8
      9maintainers:
     10  - Aswath Govindraju <a-govindraju@ti.com>
     11
     12allOf:
     13  - $ref: spi-controller.yaml#
     14
     15properties:
     16  compatible:
     17    oneOf:
     18      - items:
     19          - enum:
     20              - ti,am654-mcspi
     21              - ti,am4372-mcspi
     22          - const: ti,omap4-mcspi
     23      - items:
     24          - enum:
     25              - ti,omap2-mcspi
     26              - ti,omap4-mcspi
     27
     28  reg:
     29    maxItems: 1
     30
     31  interrupts:
     32    maxItems: 1
     33
     34  clocks:
     35    maxItems: 1
     36
     37  power-domains:
     38    maxItems: 1
     39
     40  ti,spi-num-cs:
     41    $ref: /schemas/types.yaml#/definitions/uint32
     42    description: Number of chipselect supported  by the instance.
     43    minimum: 1
     44    maximum: 4
     45
     46  ti,hwmods:
     47    $ref: /schemas/types.yaml#/definitions/string
     48    description:
     49      Must be "mcspi<n>", n being the instance number (1-based).
     50      This property is applicable only on legacy platforms mainly omap2/3
     51      and ti81xx and should not be used on other platforms.
     52    deprecated: true
     53
     54  ti,pindir-d0-out-d1-in:
     55    description:
     56      Select the D0 pin as output and D1 as input. The default is D0
     57      as input and D1 as output.
     58    type: boolean
     59
     60  dmas:
     61    description:
     62      List of DMA specifiers with the controller specific format as
     63      described in the generic DMA client binding. A tx and rx
     64      specifier is required for each chip select.
     65    minItems: 1
     66    maxItems: 8
     67
     68  dma-names:
     69    description:
     70      List of DMA request names. These strings correspond 1:1 with
     71      the DMA sepecifiers listed in dmas. The string names is to be
     72      "rxN" and "txN" for RX and TX requests, respectively. Where N
     73      is the chip select number.
     74    minItems: 1
     75    maxItems: 8
     76
     77required:
     78  - compatible
     79  - reg
     80  - interrupts
     81
     82unevaluatedProperties: false
     83
     84if:
     85  properties:
     86    compatible:
     87      enum:
     88        - ti,omap2-mcspi
     89        - ti,omap4-mcspi
     90
     91then:
     92  properties:
     93    ti,hwmods:
     94      items:
     95        - pattern: "^mcspi([1-9])$"
     96
     97else:
     98  properties:
     99    ti,hwmods: false
    100
    101examples:
    102  - |
    103    #include <dt-bindings/interrupt-controller/irq.h>
    104    #include <dt-bindings/interrupt-controller/arm-gic.h>
    105    #include <dt-bindings/soc/ti,sci_pm_domain.h>
    106
    107    spi@2100000 {
    108      compatible = "ti,am654-mcspi","ti,omap4-mcspi";
    109      reg = <0x2100000 0x400>;
    110      interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
    111      clocks = <&k3_clks 137 1>;
    112      power-domains = <&k3_pds 137 TI_SCI_PD_EXCLUSIVE>;
    113      #address-cells = <1>;
    114      #size-cells = <0>;
    115      dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
    116      dma-names = "tx0", "rx0";
    117    };