cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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qcom,spi-qcom-qspi.yaml (2044B)

      1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
      2
      3%YAML 1.2
      4---
      5$id: "http://devicetree.org/schemas/spi/qcom,spi-qcom-qspi.yaml#"
      6$schema: "http://devicetree.org/meta-schemas/core.yaml#"
      7
      8title: Qualcomm Quad Serial Peripheral Interface (QSPI)
      9
     10maintainers:
     11  - Bjorn Andersson <bjorn.andersson@linaro.org>
     12
     13description: The QSPI controller allows SPI protocol communication in single,
     14  dual, or quad wire transmission modes for read/write access to slaves such
     15  as NOR flash.
     16
     17allOf:
     18  - $ref: /schemas/spi/spi-controller.yaml#
     19
     20properties:
     21  compatible:
     22    items:
     23      - enum:
     24          - qcom,sc7180-qspi
     25          - qcom,sc7280-qspi
     26          - qcom,sdm845-qspi
     27
     28      - const: qcom,qspi-v1
     29
     30  reg:
     31    maxItems: 1
     32
     33  interrupts:
     34    maxItems: 1
     35
     36  clock-names:
     37    items:
     38      - const: iface
     39      - const: core
     40
     41  clocks:
     42    items:
     43      - description: AHB clock
     44      - description: QSPI core clock
     45
     46  interconnects:
     47    minItems: 1
     48    maxItems: 2
     49
     50  interconnect-names:
     51    minItems: 1
     52    items:
     53      - const: qspi-config
     54      - const: qspi-memory
     55
     56required:
     57  - compatible
     58  - reg
     59  - interrupts
     60  - clock-names
     61  - clocks
     62
     63unevaluatedProperties: false
     64
     65examples:
     66  - |
     67    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
     68    #include <dt-bindings/interrupt-controller/arm-gic.h>
     69
     70    soc: soc {
     71        #address-cells = <2>;
     72        #size-cells = <2>;
     73
     74        qspi: spi@88df000 {
     75            compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
     76            reg = <0 0x88df000 0 0x600>;
     77            #address-cells = <1>;
     78            #size-cells = <0>;
     79            interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
     80            clock-names = "iface", "core";
     81            clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
     82                         <&gcc GCC_QSPI_CORE_CLK>;
     83
     84            flash@0 {
     85                compatible = "jedec,spi-nor";
     86                reg = <0>;
     87                spi-max-frequency = <25000000>;
     88                spi-tx-bus-width = <2>;
     89                spi-rx-bus-width = <2>;
     90            };
     91
     92        };
     93    };
     94...