cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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rockchip-sfc.yaml (2028B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/spi/rockchip-sfc.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Rockchip Serial Flash Controller (SFC)
      8
      9maintainers:
     10  - Heiko Stuebner <heiko@sntech.de>
     11  - Chris Morgan <macromorgan@hotmail.com>
     12
     13allOf:
     14  - $ref: spi-controller.yaml#
     15
     16properties:
     17  compatible:
     18    const: rockchip,sfc
     19    description:
     20      The rockchip sfc controller is a standalone IP with version register,
     21      and the driver can handle all the feature difference inside the IP
     22      depending on the version register.
     23
     24  reg:
     25    maxItems: 1
     26
     27  interrupts:
     28    maxItems: 1
     29
     30  clocks:
     31    items:
     32      - description: Bus Clock
     33      - description: Module Clock
     34
     35  clock-names:
     36    items:
     37      - const: clk_sfc
     38      - const: hclk_sfc
     39
     40  power-domains:
     41    maxItems: 1
     42
     43  rockchip,sfc-no-dma:
     44    description: Disable DMA and utilize FIFO mode only
     45    type: boolean
     46
     47patternProperties:
     48  "^flash@[0-3]$":
     49    type: object
     50    properties:
     51      reg:
     52        minimum: 0
     53        maximum: 3
     54
     55required:
     56  - compatible
     57  - reg
     58  - interrupts
     59  - clocks
     60  - clock-names
     61
     62unevaluatedProperties: false
     63
     64examples:
     65  - |
     66    #include <dt-bindings/clock/px30-cru.h>
     67    #include <dt-bindings/interrupt-controller/arm-gic.h>
     68    #include <dt-bindings/power/px30-power.h>
     69
     70    sfc: spi@ff3a0000 {
     71        compatible = "rockchip,sfc";
     72        reg = <0xff3a0000 0x4000>;
     73        interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
     74        clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
     75        clock-names = "clk_sfc", "hclk_sfc";
     76        pinctrl-0 = <&sfc_clk &sfc_cs &sfc_bus2>;
     77        pinctrl-names = "default";
     78        power-domains = <&power PX30_PD_MMC_NAND>;
     79        #address-cells = <1>;
     80        #size-cells = <0>;
     81
     82        flash@0 {
     83            compatible = "jedec,spi-nor";
     84            reg = <0>;
     85            spi-max-frequency = <108000000>;
     86            spi-rx-bus-width = <2>;
     87            spi-tx-bus-width = <2>;
     88        };
     89    };
     90
     91...