cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

snps,dw-apb-ssi.yaml (4585B)

      1# SPDX-License-Identifier: GPL-2.0-only
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/spi/snps,dw-apb-ssi.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface
      8
      9maintainers:
     10  - Mark Brown <broonie@kernel.org>
     11
     12allOf:
     13  - $ref: "spi-controller.yaml#"
     14  - if:
     15      properties:
     16        compatible:
     17          contains:
     18            enum:
     19              - mscc,ocelot-spi
     20              - mscc,jaguar2-spi
     21    then:
     22      properties:
     23        reg:
     24          minItems: 2
     25  - if:
     26      properties:
     27        compatible:
     28          contains:
     29            enum:
     30              - baikal,bt1-sys-ssi
     31    then:
     32      properties:
     33        mux-controls:
     34          maxItems: 1
     35      required:
     36        - mux-controls
     37    else:
     38      required:
     39        - interrupts
     40
     41properties:
     42  compatible:
     43    oneOf:
     44      - description: Generic DW SPI Controller
     45        enum:
     46          - snps,dw-apb-ssi
     47          - snps,dwc-ssi-1.01a
     48      - description: Microsemi Ocelot/Jaguar2 SoC SPI Controller
     49        items:
     50          - enum:
     51              - mscc,ocelot-spi
     52              - mscc,jaguar2-spi
     53          - const: snps,dw-apb-ssi
     54      - description: Microchip Sparx5 SoC SPI Controller
     55        const: microchip,sparx5-spi
     56      - description: Amazon Alpine SPI Controller
     57        const: amazon,alpine-dw-apb-ssi
     58      - description: Renesas RZ/N1 SPI Controller
     59        items:
     60          - const: renesas,rzn1-spi
     61          - const: snps,dw-apb-ssi
     62      - description: Intel Keem Bay SPI Controller
     63        const: intel,keembay-ssi
     64      - description: Baikal-T1 SPI Controller
     65        const: baikal,bt1-ssi
     66      - description: Baikal-T1 System Boot SPI Controller
     67        const: baikal,bt1-sys-ssi
     68      - description: Canaan Kendryte K210 SoS SPI Controller
     69        const: canaan,k210-spi
     70      - description: Renesas RZ/N1 SPI Controller
     71        items:
     72          - enum:
     73              - renesas,r9a06g032-spi # RZ/N1D
     74              - renesas,r9a06g033-spi # RZ/N1S
     75          - const: renesas,rzn1-spi   # RZ/N1
     76
     77  reg:
     78    minItems: 1
     79    items:
     80      - description: DW APB SSI controller memory mapped registers
     81      - description: SPI MST region map or directly mapped SPI ROM
     82
     83  interrupts:
     84    maxItems: 1
     85
     86  clocks:
     87    minItems: 1
     88    items:
     89      - description: SPI Controller reference clock source
     90      - description: APB interface clock source
     91
     92  clock-names:
     93    minItems: 1
     94    items:
     95      - const: ssi_clk
     96      - const: pclk
     97
     98  resets:
     99    maxItems: 1
    100
    101  reset-names:
    102    const: spi
    103
    104  reg-io-width:
    105    $ref: /schemas/types.yaml#/definitions/uint32
    106    description: I/O register width (in bytes) implemented by this device
    107    default: 4
    108    enum: [ 2, 4 ]
    109
    110  num-cs:
    111    default: 4
    112    minimum: 1
    113    maximum: 4
    114
    115  dmas:
    116    items:
    117      - description: TX DMA Channel
    118      - description: RX DMA Channel
    119
    120  dma-names:
    121    items:
    122      - const: tx
    123      - const: rx
    124
    125  rx-sample-delay-ns:
    126    default: 0
    127    description: Default value of the rx-sample-delay-ns property.
    128      This value will be used if the property is not explicitly defined
    129      for a SPI slave device. See below.
    130
    131patternProperties:
    132  "^.*@[0-9a-f]+$":
    133    type: object
    134    properties:
    135      reg:
    136        minimum: 0
    137        maximum: 3
    138
    139      spi-rx-bus-width:
    140        const: 1
    141
    142      spi-tx-bus-width:
    143        const: 1
    144
    145      rx-sample-delay-ns:
    146        description: SPI Rx sample delay offset, unit is nanoseconds.
    147          The delay from the default sample time before the actual
    148          sample of the rxd input signal occurs. The "rx_sample_delay"
    149          is an optional feature of the designware controller, and the
    150          upper limit is also subject to controller configuration.
    151
    152unevaluatedProperties: false
    153
    154required:
    155  - compatible
    156  - reg
    157  - "#address-cells"
    158  - "#size-cells"
    159  - clocks
    160
    161examples:
    162  - |
    163    spi@fff00000 {
    164      compatible = "snps,dw-apb-ssi";
    165      reg = <0xfff00000 0x1000>;
    166      #address-cells = <1>;
    167      #size-cells = <0>;
    168      interrupts = <0 154 4>;
    169      clocks = <&spi_m_clk>;
    170      num-cs = <2>;
    171      cs-gpios = <&gpio0 13 0>,
    172                 <&gpio0 14 0>;
    173      rx-sample-delay-ns = <3>;
    174      flash@1 {
    175        compatible = "spi-nand";
    176        reg = <1>;
    177        rx-sample-delay-ns = <7>;
    178      };
    179    };
    180  - |
    181    spi@1f040100 {
    182      compatible = "baikal,bt1-sys-ssi";
    183      reg = <0x1f040100 0x900>,
    184            <0x1c000000 0x1000000>;
    185      #address-cells = <1>;
    186      #size-cells = <0>;
    187      mux-controls = <&boot_mux>;
    188      clocks = <&ccu_sys>;
    189      clock-names = "ssi_clk";
    190    };
    191...