cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

spi-fsl-dspi.txt (2058B)

      1ARM Freescale DSPI controller
      2
      3Required properties:
      4- compatible : must be one of:
      5	"fsl,vf610-dspi",
      6	"fsl,ls1021a-v1.0-dspi",
      7	"fsl,ls1012a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"),
      8	"fsl,ls1028a-dspi",
      9	"fsl,ls1043a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"),
     10	"fsl,ls1046a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"),
     11	"fsl,ls1088a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"),
     12	"fsl,ls2080a-dspi" (optionally followed by "fsl,ls2085a-dspi"),
     13	"fsl,ls2085a-dspi",
     14	"fsl,lx2160a-dspi",
     15- reg : Offset and length of the register set for the device
     16- interrupts : Should contain SPI controller interrupt
     17- clocks: from common clock binding: handle to dspi clock.
     18- clock-names: from common clock binding: Shall be "dspi".
     19- pinctrl-0: pin control group to be used for this controller.
     20- pinctrl-names: must contain a "default" entry.
     21- spi-num-chipselects : the number of the chipselect signals.
     22
     23Optional property:
     24- big-endian: If present the dspi device's registers are implemented
     25  in big endian mode.
     26- bus-num : the slave chip chipselect signal number.
     27
     28Optional SPI slave node properties:
     29- fsl,spi-cs-sck-delay: a delay in nanoseconds between activating chip
     30  select and the start of clock signal, at the start of a transfer.
     31- fsl,spi-sck-cs-delay: a delay in nanoseconds between stopping the clock
     32  signal and deactivating chip select, at the end of a transfer.
     33
     34Example:
     35
     36dspi0@4002c000 {
     37	#address-cells = <1>;
     38	#size-cells = <0>;
     39	compatible = "fsl,vf610-dspi";
     40	reg = <0x4002c000 0x1000>;
     41	interrupts = <0 67 0x04>;
     42	clocks = <&clks VF610_CLK_DSPI0>;
     43	clock-names = "dspi";
     44	spi-num-chipselects = <5>;
     45	bus-num = <0>;
     46	pinctrl-names = "default";
     47	pinctrl-0 = <&pinctrl_dspi0_1>;
     48	big-endian;
     49
     50	sflash: at26df081a@0 {
     51		#address-cells = <1>;
     52		#size-cells = <1>;
     53		compatible = "atmel,at26df081a";
     54		spi-max-frequency = <16000000>;
     55		spi-cpol;
     56		spi-cpha;
     57		reg = <0>;
     58		linux,modalias = "m25p80";
     59		modal = "at26df081a";
     60		fsl,spi-cs-sck-delay = <100>;
     61		fsl,spi-sck-cs-delay = <50>;
     62	};
     63};
     64
     65