cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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spi-octeon.txt (763B)

      1Cavium, Inc. OCTEON SOC SPI master controller.
      2
      3Required properties:
      4- compatible : "cavium,octeon-3010-spi"
      5- reg : The register base for the controller.
      6- interrupts : One interrupt, used by the controller.
      7- #address-cells : <1>, as required by generic SPI binding.
      8- #size-cells : <0>, also as required by generic SPI binding.
      9
     10Child nodes as per the generic SPI binding.
     11
     12Example:
     13
     14	spi@1070000001000 {
     15		compatible = "cavium,octeon-3010-spi";
     16		reg = <0x10700 0x00001000 0x0 0x100>;
     17		interrupts = <0 58>;
     18		#address-cells = <1>;
     19		#size-cells = <0>;
     20
     21		eeprom@0 {
     22			compatible = "st,m95256", "atmel,at25";
     23			reg = <0>;
     24			spi-max-frequency = <5000000>;
     25			spi-cpha;
     26			spi-cpol;
     27
     28			pagesize = <64>;
     29			size = <32768>;
     30			address-width = <16>;
     31		};
     32	};
     33