cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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spi-sprd.txt (1161B)


      1Spreadtrum SPI Controller
      2
      3Required properties:
      4- compatible: Should be "sprd,sc9860-spi".
      5- reg: Offset and length of SPI controller register space.
      6- interrupts: Should contain SPI interrupt.
      7- clock-names: Should contain following entries:
      8	"spi" for SPI clock,
      9	"source" for SPI source (parent) clock,
     10	"enable" for SPI module enable clock.
     11- clocks: List of clock input name strings sorted in the same order
     12	as the clock-names property.
     13- #address-cells: The number of cells required to define a chip select
     14	address on the SPI bus. Should be set to 1.
     15- #size-cells: Should be set to 0.
     16
     17Optional properties:
     18dma-names: Should contain names of the SPI used DMA channel.
     19dmas: Should contain DMA channels and DMA slave ids which the SPI used
     20	sorted in the same order as the dma-names property.
     21
     22Example:
     23spi0: spi@70a00000{
     24	compatible = "sprd,sc9860-spi";
     25	reg = <0 0x70a00000 0 0x1000>;
     26	interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
     27	clock-names = "spi", "source","enable";
     28	clocks = <&clk_spi0>, <&ext_26m>, <&clk_ap_apb_gates 5>;
     29	dma-names = "rx_chn", "tx_chn";
     30	dmas = <&apdma 11 11>, <&apdma 12 12>;
     31	#address-cells = <1>;
     32	#size-cells = <0>;
     33};