cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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spi-synquacer.txt (916B)


      1* Socionext Synquacer HS-SPI bindings
      2
      3Required Properties:
      4- compatible: should be "socionext,synquacer-spi"
      5- reg: physical base address of the controller and length of memory mapped
      6       region.
      7- interrupts: should contain the "spi_rx", "spi_tx" and "spi_fault" interrupts.
      8- clocks: core clock iHCLK. Optional rate clock iPCLK (default is iHCLK)
      9- clock-names: Shall be "iHCLK" and "iPCLK" respectively
     10
     11Optional Properties:
     12- socionext,use-rtm: boolean, if required to use "retimed clock" for RX
     13- socionext,set-aces: boolean, if same active clock edges field to be set.
     14
     15Example:
     16
     17	spi0: spi@ff110000 {
     18		compatible = "socionext,synquacer-spi";
     19		reg = <0xff110000 0x1000>;
     20		interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
     21			     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
     22			     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
     23		clocks = <&clk_hsspi>;
     24		clock-names = "iHCLK";
     25		socionext,use-rtm;
     26		socionext,set-aces;
     27	};