cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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spi_atmel.txt (980B)


      1Atmel SPI device
      2
      3Required properties:
      4- compatible : should be "atmel,at91rm9200-spi" or "microchip,sam9x60-spi".
      5- reg: Address and length of the register set for the device
      6- interrupts: Should contain spi interrupt
      7- cs-gpios: chipselects (optional for SPI controller version >= 2 with the
      8  Chip Select Active After Transfer feature).
      9- clock-names: tuple listing input clock names.
     10	Required elements: "spi_clk"
     11- clocks: phandles to input clocks.
     12
     13Optional properties:
     14- atmel,fifo-size: maximum number of data the RX and TX FIFOs can store for FIFO
     15  capable SPI controllers.
     16
     17Example:
     18
     19spi1: spi@fffcc000 {
     20	compatible = "atmel,at91rm9200-spi";
     21	reg = <0xfffcc000 0x4000>;
     22	interrupts = <13 4 5>;
     23	#address-cells = <1>;
     24	#size-cells = <0>;
     25	clocks = <&spi1_clk>;
     26	clock-names = "spi_clk";
     27	cs-gpios = <&pioB 3 0>;
     28	atmel,fifo-size = <32>;
     29
     30	mmc-slot@0 {
     31		compatible = "mmc-spi-slot";
     32		reg = <0>;
     33		gpios = <&pioC 4 0>;	/* CD */
     34		spi-max-frequency = <25000000>;
     35	};
     36};