cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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ti_qspi.txt (1784B)

      1TI QSPI controller.
      2
      3Required properties:
      4- compatible : should be "ti,dra7xxx-qspi" or "ti,am4372-qspi".
      5- reg: Should contain QSPI registers location and length.
      6- reg-names: Should contain the resource reg names.
      7	- qspi_base: Qspi configuration register Address space
      8	- qspi_mmap: Memory mapped Address space
      9	- (optional) qspi_ctrlmod: Control module Address space
     10- interrupts: should contain the qspi interrupt number.
     11- #address-cells, #size-cells : Must be present if the device has sub-nodes
     12- ti,hwmods: Name of the hwmod associated to the QSPI
     13
     14Recommended properties:
     15- spi-max-frequency: Definition as per
     16                     Documentation/devicetree/bindings/spi/spi-bus.txt
     17
     18Optional properties:
     19- syscon-chipselects: Handle to system control region contains QSPI
     20		      chipselect register and offset of that register.
     21
     22NOTE: TI QSPI controller requires different pinmux and IODelay
     23parameters for Mode-0 and Mode-3 operations, which needs to be set up by
     24the bootloader (U-Boot). Default configuration only supports Mode-0
     25operation. Hence, "spi-cpol" and "spi-cpha" DT properties cannot be
     26specified in the slave nodes of TI QSPI controller without appropriate
     27modification to bootloader.
     28
     29Example:
     30
     31For am4372:
     32qspi: qspi@47900000 {
     33	compatible = "ti,am4372-qspi";
     34	reg = <0x47900000 0x100>, <0x30000000 0x4000000>;
     35	reg-names = "qspi_base", "qspi_mmap";
     36	#address-cells = <1>;
     37	#size-cells = <0>;
     38	spi-max-frequency = <25000000>;
     39	ti,hwmods = "qspi";
     40};
     41
     42For dra7xx:
     43qspi: qspi@4b300000 {
     44	compatible = "ti,dra7xxx-qspi";
     45	reg = <0x4b300000 0x100>,
     46	      <0x5c000000 0x4000000>,
     47	reg-names = "qspi_base", "qspi_mmap";
     48	syscon-chipselects = <&scm_conf 0x558>;
     49	#address-cells = <1>;
     50	#size-cells = <0>;
     51	spi-max-frequency = <48000000>;
     52	ti,hwmods = "qspi";
     53};