cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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rockchip-thermal.yaml (2314B)

      1# SPDX-License-Identifier: GPL-2.0-only
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/thermal/rockchip-thermal.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Temperature Sensor ADC (TSADC) on Rockchip SoCs
      8
      9maintainers:
     10  - Heiko Stuebner <heiko@sntech.de>
     11
     12properties:
     13  compatible:
     14    enum:
     15      - rockchip,px30-tsadc
     16      - rockchip,rk3228-tsadc
     17      - rockchip,rk3288-tsadc
     18      - rockchip,rk3328-tsadc
     19      - rockchip,rk3368-tsadc
     20      - rockchip,rk3399-tsadc
     21      - rockchip,rk3568-tsadc
     22      - rockchip,rv1108-tsadc
     23
     24  reg:
     25    maxItems: 1
     26
     27  interrupts:
     28    maxItems: 1
     29
     30  clocks:
     31    minItems: 2
     32    maxItems: 2
     33
     34  clock-names:
     35    items:
     36      - const: tsadc
     37      - const: apb_pclk
     38
     39  resets:
     40    minItems: 1
     41    maxItems: 3
     42
     43  reset-names:
     44    minItems: 1
     45    items:
     46      - const: tsadc-apb
     47      - const: tsadc
     48      - const: tsadc-phy
     49
     50  "#thermal-sensor-cells":
     51    const: 1
     52
     53  rockchip,grf:
     54    description: The phandle of the syscon node for the general register file.
     55    $ref: /schemas/types.yaml#/definitions/phandle
     56
     57  rockchip,hw-tshut-temp:
     58    description: The hardware-controlled shutdown temperature value.
     59    $ref: /schemas/types.yaml#/definitions/uint32
     60
     61  rockchip,hw-tshut-mode:
     62    description: The hardware-controlled shutdown mode 0:CRU 1:GPIO.
     63    $ref: /schemas/types.yaml#/definitions/uint32
     64    enum: [0, 1]
     65
     66  rockchip,hw-tshut-polarity:
     67    description: The hardware-controlled active polarity 0:LOW 1:HIGH.
     68    $ref: /schemas/types.yaml#/definitions/uint32
     69    enum: [0, 1]
     70
     71required:
     72  - compatible
     73  - reg
     74  - interrupts
     75  - clocks
     76  - clock-names
     77  - resets
     78  - "#thermal-sensor-cells"
     79
     80additionalProperties: false
     81
     82examples:
     83  - |
     84    #include <dt-bindings/interrupt-controller/arm-gic.h>
     85    #include <dt-bindings/clock/rk3288-cru.h>
     86
     87    tsadc: tsadc@ff280000 {
     88        compatible = "rockchip,rk3288-tsadc";
     89        reg = <0xff280000 0x100>;
     90        interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
     91        clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
     92        clock-names = "tsadc", "apb_pclk";
     93        resets = <&cru SRST_TSADC>;
     94        reset-names = "tsadc-apb";
     95        #thermal-sensor-cells = <1>;
     96        rockchip,hw-tshut-temp = <95000>;
     97        rockchip,hw-tshut-mode = <0>;
     98        rockchip,hw-tshut-polarity = <0>;
     99    };