cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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allwinner,sun5i-a13-hstimer.yaml (1472B)

      1# SPDX-License-Identifier: GPL-2.0
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/timer/allwinner,sun5i-a13-hstimer.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Allwinner A13 High-Speed Timer Device Tree Bindings
      8
      9maintainers:
     10  - Chen-Yu Tsai <wens@csie.org>
     11  - Maxime Ripard <mripard@kernel.org>
     12
     13properties:
     14  compatible:
     15    oneOf:
     16      - const: allwinner,sun5i-a13-hstimer
     17      - const: allwinner,sun7i-a20-hstimer
     18      - items:
     19          - const: allwinner,sun6i-a31-hstimer
     20          - const: allwinner,sun7i-a20-hstimer
     21
     22  reg:
     23    maxItems: 1
     24
     25  interrupts:
     26    minItems: 2
     27    items:
     28      - description: Timer 0 Interrupt
     29      - description: Timer 1 Interrupt
     30      - description: Timer 2 Interrupt
     31      - description: Timer 3 Interrupt
     32
     33  clocks:
     34    maxItems: 1
     35
     36  resets:
     37    maxItems: 1
     38
     39required:
     40  - compatible
     41  - reg
     42  - interrupts
     43  - clocks
     44
     45if:
     46  properties:
     47    compatible:
     48      const: allwinner,sun5i-a13-hstimer
     49
     50then:
     51  properties:
     52    interrupts:
     53      minItems: 2
     54      maxItems: 2
     55
     56else:
     57  properties:
     58    interrupts:
     59      minItems: 4
     60      maxItems: 4
     61
     62additionalProperties: false
     63
     64examples:
     65  - |
     66    timer@1c60000 {
     67        compatible = "allwinner,sun7i-a20-hstimer";
     68        reg = <0x01c60000 0x1000>;
     69        interrupts = <0 51 1>,
     70                     <0 52 1>,
     71                     <0 53 1>,
     72                     <0 54 1>;
     73        clocks = <&ahb1_gates 19>;
     74        resets = <&ahb1rst 19>;
     75    };
     76
     77...