cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

ingenic,sysost.yaml (1155B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/timer/ingenic,sysost.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Bindings for SYSOST in Ingenic XBurst family SoCs
      8
      9maintainers:
     10  - 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
     11
     12description:
     13  The SYSOST in an Ingenic SoC provides one 64bit timer for clocksource
     14  and one or more 32bit timers for clockevent.
     15
     16properties:
     17  "#clock-cells":
     18    const: 1
     19
     20  compatible:
     21    enum:
     22      - ingenic,x1000-ost
     23      - ingenic,x2000-ost
     24
     25  reg:
     26    maxItems: 1
     27
     28  clocks:
     29    maxItems: 1
     30
     31  clock-names:
     32    const: ost
     33
     34  interrupts:
     35    maxItems: 1
     36
     37required:
     38  - "#clock-cells"
     39  - compatible
     40  - reg
     41  - clocks
     42  - clock-names
     43  - interrupts
     44
     45additionalProperties: false
     46
     47examples:
     48  - |
     49    #include <dt-bindings/clock/ingenic,x1000-cgu.h>
     50
     51    ost: timer@12000000 {
     52        compatible = "ingenic,x1000-ost";
     53        reg = <0x12000000 0x3c>;
     54
     55        #clock-cells = <1>;
     56
     57        clocks = <&cgu X1000_CLK_OST>;
     58        clock-names = "ost";
     59
     60        interrupt-parent = <&cpuintc>;
     61        interrupts = <3>;
     62    };
     63...