cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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lsi,zevio-timer.txt (719B)

      1TI-NSPIRE timer
      2
      3Required properties:
      4
      5- compatible : should be "lsi,zevio-timer".
      6- reg : The physical base address and size of the timer (always first).
      7- clocks: phandle to the source clock.
      8
      9Optional properties:
     10
     11- interrupts : The interrupt number of the first timer.
     12- reg : The interrupt acknowledgement registers
     13	(always after timer base address)
     14
     15If any of the optional properties are not given, the timer is added as a
     16clock-source only.
     17
     18Example:
     19
     20timer {
     21	compatible = "lsi,zevio-timer";
     22	reg = <0x900D0000 0x1000>, <0x900A0020 0x8>;
     23	interrupts = <19>;
     24	clocks = <&timer_clk>;
     25};
     26
     27Example (no clock-events):
     28
     29timer {
     30	compatible = "lsi,zevio-timer";
     31	reg = <0x900D0000 0x1000>;
     32	clocks = <&timer_clk>;
     33};