cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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ti,davinci-timer.txt (1386B)


      1* Device tree bindings for Texas Instruments DaVinci timer
      2
      3This document provides bindings for the 64-bit timer in the DaVinci
      4architecture devices. The timer can be configured as a general-purpose 64-bit
      5timer, dual general-purpose 32-bit timers. When configured as dual 32-bit
      6timers, each half can operate in conjunction (chain mode) or independently
      7(unchained mode) of each other.
      8
      9The timer is a free running up-counter and can generate interrupts when the
     10counter reaches preset counter values.
     11
     12Also see ../watchdog/davinci-wdt.txt for timers that are configurable as
     13watchdog timers.
     14
     15Required properties:
     16
     17- compatible : should be "ti,da830-timer".
     18- reg : specifies base physical address and count of the registers.
     19- interrupts : interrupts generated by the timer.
     20- interrupt-names: should be "tint12", "tint34", "cmpint0", "cmpint1",
     21		   "cmpint2", "cmpint3", "cmpint4", "cmpint5", "cmpint6",
     22		   "cmpint7" ("cmpintX" may be omitted if not present in the
     23		   hardware).
     24- clocks : the clock feeding the timer clock.
     25
     26Example:
     27
     28	clocksource: timer@20000 {
     29		compatible = "ti,da830-timer";
     30		reg = <0x20000 0x1000>;
     31		interrupts = <21>, <22>, <74>, <75>, <76>, <77>, <78>, <79>,
     32			     <80>, <81>;
     33		interrupt-names = "tint12", "tint34", "cmpint0", "cmpint1",
     34				  "cmpint2", "cmpint3", "cmpint4", "cmpint5",
     35				  "cmpint6", "cmpint7";
     36		clocks = <&pll0_auxclk>;
     37	};