cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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ti,keystone-timer.txt (975B)


      1* Device tree bindings for Texas instruments Keystone timer
      2
      3This document provides bindings for the 64-bit timer in the KeyStone
      4architecture devices. The timer can be configured as a general-purpose 64-bit
      5timer, dual general-purpose 32-bit timers. When configured as dual 32-bit
      6timers, each half can operate in conjunction (chain mode) or independently
      7(unchained mode) of each other.
      8
      9It is global timer is a free running up-counter and can generate interrupt
     10when the counter reaches preset counter values.
     11
     12Documentation:
     13https://www.ti.com/lit/ug/sprugv5a/sprugv5a.pdf
     14
     15Required properties:
     16
     17- compatible : should be "ti,keystone-timer".
     18- reg : specifies base physical address and count of the registers.
     19- interrupts : interrupt generated by the timer.
     20- clocks : the clock feeding the timer clock.
     21
     22Example:
     23
     24timer@22f0000 {
     25	compatible = "ti,keystone-timer";
     26	reg = <0x022f0000 0x80>;
     27	interrupts = <GIC_SPI 110 IRQ_TYPE_EDGE_RISING>;
     28	clocks = <&clktimer15>;
     29};