cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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xlnx,xps-timer.yaml (1846B)

      1# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/timer/xlnx,xps-timer.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Xilinx LogiCORE IP AXI Timer Device Tree Binding
      8
      9maintainers:
     10  - Sean Anderson <sean.anderson@seco.com>
     11
     12properties:
     13  compatible:
     14    contains:
     15      const: xlnx,xps-timer-1.00.a
     16
     17  clocks:
     18    maxItems: 1
     19
     20  clock-names:
     21    const: s_axi_aclk
     22
     23  interrupts:
     24    maxItems: 1
     25
     26  reg:
     27    maxItems: 1
     28
     29  '#pwm-cells': true
     30
     31  xlnx,count-width:
     32    $ref: /schemas/types.yaml#/definitions/uint32
     33    enum: [8, 16, 32]
     34    default: 32
     35    description:
     36      The width of the counter(s), in bits.
     37
     38  xlnx,one-timer-only:
     39    $ref: /schemas/types.yaml#/definitions/uint32
     40    enum: [ 0, 1 ]
     41    description:
     42      Whether only one timer is present in this block.
     43
     44required:
     45  - compatible
     46  - reg
     47  - xlnx,one-timer-only
     48
     49allOf:
     50  - if:
     51      required:
     52        - '#pwm-cells'
     53    then:
     54      allOf:
     55        - required:
     56            - clocks
     57        - properties:
     58            xlnx,one-timer-only:
     59              const: 0
     60    else:
     61      required:
     62        - interrupts
     63  - if:
     64      required:
     65        - clocks
     66    then:
     67      required:
     68        - clock-names
     69
     70additionalProperties: false
     71
     72examples:
     73  - |
     74    timer@800e0000 {
     75        clock-names = "s_axi_aclk";
     76        clocks = <&zynqmp_clk 71>;
     77        compatible = "xlnx,xps-timer-1.00.a";
     78        reg = <0x800e0000 0x10000>;
     79        interrupts = <0 39 2>;
     80        xlnx,count-width = <16>;
     81        xlnx,one-timer-only = <0x0>;
     82    };
     83
     84    timer@800f0000 {
     85        #pwm-cells = <0>;
     86        clock-names = "s_axi_aclk";
     87        clocks = <&zynqmp_clk 71>;
     88        compatible = "xlnx,xps-timer-1.00.a";
     89        reg = <0x800e0000 0x10000>;
     90        xlnx,count-width = <32>;
     91        xlnx,one-timer-only = <0x0>;
     92    };