cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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cdns,ufshc.yaml (1380B)

      1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/ufs/cdns,ufshc.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Cadence Universal Flash Storage (UFS) Controller
      8
      9maintainers:
     10  - Jan Kotas <jank@cadence.com>
     11
     12# Select only our matches, not all jedec,ufs-2.0
     13select:
     14  properties:
     15    compatible:
     16      contains:
     17        enum:
     18          - cdns,ufshc
     19          - cdns,ufshc-m31-16nm
     20  required:
     21    - compatible
     22
     23allOf:
     24  - $ref: ufs-common.yaml
     25
     26properties:
     27  compatible:
     28    items:
     29      - enum:
     30          - cdns,ufshc
     31            # CDNS UFS HC + M31 16nm PHY
     32          - cdns,ufshc-m31-16nm
     33      - const: jedec,ufs-2.0
     34
     35  clocks:
     36    minItems: 1
     37    maxItems: 3
     38
     39  clock-names:
     40    minItems: 1
     41    items:
     42      - const: core_clk
     43      - const: phy_clk
     44      - const: ref_clk
     45
     46  power-domains:
     47    maxItems: 1
     48
     49  reg:
     50    maxItems: 1
     51
     52required:
     53  - compatible
     54  - clocks
     55  - clock-names
     56  - reg
     57
     58unevaluatedProperties: false
     59
     60examples:
     61  - |
     62    #include <dt-bindings/interrupt-controller/arm-gic.h>
     63
     64    ufs@fd030000 {
     65        compatible = "cdns,ufshc", "jedec,ufs-2.0";
     66        reg = <0xfd030000 0x10000>;
     67        interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
     68        freq-table-hz = <0 0>, <0 0>;
     69        clocks = <&ufs_core_clk>, <&ufs_phy_clk>;
     70        clock-names = "core_clk", "phy_clk";
     71    };