cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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ohci-st.txt (1149B)

      1ST USB OHCI controller
      2
      3Required properties:
      4
      5 - compatible		: must be "st,st-ohci-300x"
      6 - reg			: physical base addresses of the controller and length of memory mapped
      7			  region
      8 - interrupts		: one OHCI controller interrupt should be described here
      9 - clocks		: phandle list of usb clocks
     10 - clock-names		: should be "ic" for interconnect clock and "clk48"
     11See: Documentation/devicetree/bindings/clock/clock-bindings.txt
     12
     13 - phys			: phandle for the PHY device
     14 - phy-names		: should be "usb"
     15
     16 - resets		: phandle to the powerdown and reset controller for the USB IP
     17 - reset-names		: should be "power" and "softreset".
     18See: Documentation/devicetree/bindings/reset/st,stih407-powerdown.yaml
     19See: Documentation/devicetree/bindings/reset/reset.txt
     20
     21Example:
     22
     23	ohci0: usb@fe1ffc00 {
     24		compatible = "st,st-ohci-300x";
     25		reg = <0xfe1ffc00 0x100>;
     26		interrupts = <GIC_SPI 149 IRQ_TYPE_NONE>;
     27		clocks = <&clk_s_a1_ls 0>,
     28			 <&clockgen_b0 0>;
     29		clock-names = "ic", "clk48";
     30		phys = <&usb2_phy>;
     31		phy-names = "usb";
     32
     33		resets = <&powerdown STIH416_USB0_POWERDOWN>,
     34			 <&softreset STIH416_USB0_SOFTRESET>;
     35		reset-names = "power", "softreset";
     36	};