cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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omap-usb.txt (2713B)

      1OMAP GLUE AND OTHER OMAP SPECIFIC COMPONENTS
      2
      3OMAP MUSB GLUE
      4 - compatible : Should be "ti,omap4-musb" or "ti,omap3-musb"
      5 - ti,hwmods : must be "usb_otg_hs"
      6 - multipoint : Should be "1" indicating the musb controller supports
      7   multipoint. This is a MUSB configuration-specific setting.
      8 - num-eps : Specifies the number of endpoints. This is also a
      9   MUSB configuration-specific setting. Should be set to "16"
     10 - ram-bits : Specifies the ram address size. Should be set to "12"
     11 - interface-type : This is a board specific setting to describe the type of
     12   interface between the controller and the phy. It should be "0" or "1"
     13   specifying ULPI and UTMI respectively.
     14 - mode : Should be "3" to represent OTG. "1" signifies HOST and "2"
     15   represents PERIPHERAL.
     16 - power : Should be "50". This signifies the controller can supply up to
     17   100mA when operating in host mode.
     18 - usb-phy : the phandle for the PHY device
     19 - phys : the phandle for the PHY device (used by generic PHY framework)
     20 - phy-names : the names of the PHY corresponding to the PHYs present in the
     21   *phy* phandle.
     22
     23Optional properties:
     24 - ctrl-module : phandle of the control module this glue uses to write to
     25   mailbox
     26
     27SOC specific device node entry
     28usb_otg_hs: usb_otg_hs@4a0ab000 {
     29	compatible = "ti,omap4-musb";
     30	ti,hwmods = "usb_otg_hs";
     31	multipoint = <1>;
     32	num-eps = <16>;
     33	ram-bits = <12>;
     34	ctrl-module = <&omap_control_usb>;
     35	phys = <&usb2_phy>;
     36	phy-names = "usb2-phy";
     37};
     38
     39Board specific device node entry
     40&usb_otg_hs {
     41	interface-type = <1>;
     42	mode = <3>;
     43	power = <50>;
     44};
     45
     46OMAP DWC3 GLUE
     47 - compatible : Should be
     48	* "ti,dwc3" for OMAP5 and DRA7
     49	* "ti,am437x-dwc3" for AM437x
     50 - ti,hwmods : Should be "usb_otg_ss"
     51 - reg : Address and length of the register set for the device.
     52 - interrupts : The irq number of this device that is used to interrupt the
     53   MPU
     54 - #address-cells, #size-cells : Must be present if the device has sub-nodes
     55 - utmi-mode : controls the source of UTMI/PIPE status for VBUS and OTG ID.
     56   It should be set to "1" for HW mode and "2" for SW mode.
     57 - ranges: the child address space are mapped 1:1 onto the parent address space
     58
     59Optional Properties:
     60 - extcon : phandle for the extcon device omap dwc3 uses to detect
     61   connect/disconnect events.
     62 - vbus-supply : phandle to the regulator device tree node if needed.
     63
     64Sub-nodes:
     65The dwc3 core should be added as subnode to omap dwc3 glue.
     66- dwc3 :
     67   The binding details of dwc3 can be found in:
     68   Documentation/devicetree/bindings/usb/snps,dwc3.yaml
     69
     70omap_dwc3 {
     71	compatible = "ti,dwc3";
     72	ti,hwmods = "usb_otg_ss";
     73	reg = <0x4a020000 0x1ff>;
     74	interrupts = <0 93 4>;
     75	#address-cells = <1>;
     76	#size-cells = <1>;
     77	utmi-mode = <2>;
     78	ranges;
     79};
     80