cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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ti,rti-wdt.yaml (1504B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/watchdog/ti,rti-wdt.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Texas Instruments K3 SoC Watchdog Timer
      8
      9maintainers:
     10  - Tero Kristo <t-kristo@ti.com>
     11
     12description:
     13  The TI K3 SoC watchdog timer is implemented via the RTI (Real Time
     14  Interrupt) IP module. This timer adds a support for windowed watchdog
     15  mode, which will signal an error if it is pinged outside the watchdog
     16  time window, meaning either too early or too late. The error signal
     17  generated can be routed to either interrupt a safety controller or
     18  to directly reset the SoC.
     19
     20allOf:
     21  - $ref: "watchdog.yaml#"
     22
     23properties:
     24  compatible:
     25    enum:
     26      - ti,j7-rti-wdt
     27
     28  reg:
     29    maxItems: 1
     30
     31  clocks:
     32    maxItems: 1
     33
     34  power-domains:
     35    maxItems: 1
     36
     37required:
     38  - compatible
     39  - reg
     40  - clocks
     41  - power-domains
     42
     43unevaluatedProperties: false
     44
     45examples:
     46  - |
     47    /*
     48     * RTI WDT in main domain on J721e SoC. Assigned clocks are used to
     49     * select the source clock for the watchdog, forcing it to tick with
     50     * a 32kHz clock in this case.
     51     */
     52    #include <dt-bindings/soc/ti,sci_pm_domain.h>
     53
     54    watchdog@2200000 {
     55        compatible = "ti,j7-rti-wdt";
     56        reg = <0x2200000 0x100>;
     57        clocks = <&k3_clks 252 1>;
     58        power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>;
     59        assigned-clocks = <&k3_clks 252 1>;
     60        assigned-clock-parents = <&k3_clks 252 5>;
     61    };