cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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emc1403.rst (2476B)

      1Kernel driver emc1403
      2=====================
      3
      4Supported chips:
      5
      6  * SMSC / Microchip EMC1402, EMC1412
      7
      8    Addresses scanned: I2C 0x18, 0x1c, 0x29, 0x4c, 0x4d, 0x5c
      9
     10    Prefix: 'emc1402'
     11
     12    Datasheets:
     13
     14	- http://ww1.microchip.com/downloads/en/DeviceDoc/1412.pdf
     15	- https://ww1.microchip.com/downloads/en/DeviceDoc/1402.pdf
     16
     17  * SMSC / Microchip EMC1403, EMC1404, EMC1413, EMC1414
     18
     19    Addresses scanned: I2C 0x18, 0x29, 0x4c, 0x4d
     20
     21    Prefix: 'emc1403', 'emc1404'
     22
     23    Datasheets:
     24
     25	- http://ww1.microchip.com/downloads/en/DeviceDoc/1403_1404.pdf
     26	- http://ww1.microchip.com/downloads/en/DeviceDoc/1413_1414.pdf
     27
     28  * SMSC / Microchip EMC1422
     29
     30    Addresses scanned: I2C 0x4c
     31
     32    Prefix: 'emc1422'
     33
     34    Datasheet:
     35
     36	- https://ww1.microchip.com/downloads/en/DeviceDoc/1422.pdf
     37
     38  * SMSC / Microchip EMC1423, EMC1424
     39
     40    Addresses scanned: I2C 0x4c
     41
     42    Prefix: 'emc1423', 'emc1424'
     43
     44    Datasheet:
     45
     46	- https://ww1.microchip.com/downloads/en/DeviceDoc/1423_1424.pdf
     47
     48Author:
     49    Kalhan Trisal <kalhan.trisal@intel.com
     50
     51
     52Description
     53-----------
     54
     55The Standard Microsystems Corporation (SMSC) / Microchip EMC14xx chips
     56contain up to four temperature sensors. EMC14x2 support two sensors
     57(one internal, one external). EMC14x3 support three sensors (one internal,
     58two external), and EMC14x4 support four sensors (one internal, three
     59external).
     60
     61The chips implement three limits for each sensor: low (tempX_min), high
     62(tempX_max) and critical (tempX_crit.) The chips also implement an
     63hysteresis mechanism which applies to all limits. The relative difference
     64is stored in a single register on the chip, which means that the relative
     65difference between the limit and its hysteresis is always the same for
     66all three limits.
     67
     68This implementation detail implies the following:
     69
     70* When setting a limit, its hysteresis will automatically follow, the
     71  difference staying unchanged. For example, if the old critical limit
     72  was 80 degrees C, and the hysteresis was 75 degrees C, and you change
     73  the critical limit to 90 degrees C, then the hysteresis will
     74  automatically change to 85 degrees C.
     75* The hysteresis values can't be set independently. We decided to make
     76  only temp1_crit_hyst writable, while all other hysteresis attributes
     77  are read-only. Setting temp1_crit_hyst writes the difference between
     78  temp1_crit_hyst and temp1_crit into the chip, and the same relative
     79  hysteresis applies automatically to all other limits.
     80* The limits should be set before the hysteresis.