i2c-mlxcpld.rst (1904B)
1================== 2Driver i2c-mlxcpld 3================== 4 5Author: Michael Shych <michaelsh@mellanox.com> 6 7This is the Mellanox I2C controller logic, implemented in Lattice CPLD 8device. 9 10Device supports: 11 - Master mode. 12 - One physical bus. 13 - Polling mode. 14 15This controller is equipped within the next Mellanox systems: 16"msx6710", "msx6720", "msb7700", "msn2700", "msx1410", "msn2410", "msb7800", 17"msn2740", "msn2100". 18 19The next transaction types are supported: 20 - Receive Byte/Block. 21 - Send Byte/Block. 22 - Read Byte/Block. 23 - Write Byte/Block. 24 25Registers: 26 27=============== === ======================================================================= 28CPBLTY 0x0 - capability reg. 29 Bits [6:5] - transaction length. b01 - 72B is supported, 30 36B in other case. 31 Bit 7 - SMBus block read support. 32CTRL 0x1 - control reg. 33 Resets all the registers. 34HALF_CYC 0x4 - cycle reg. 35 Configure the width of I2C SCL half clock cycle (in 4 LPC_CLK 36 units). 37I2C_HOLD 0x5 - hold reg. 38 OE (output enable) is delayed by value set to this register 39 (in LPC_CLK units) 40CMD 0x6 - command reg. 41 Bit 0, 0 = write, 1 = read. 42 Bits [7:1] - the 7bit Address of the I2C device. 43 It should be written last as it triggers an I2C transaction. 44NUM_DATA 0x7 - data size reg. 45 Number of data bytes to write in read transaction 46NUM_ADDR 0x8 - address reg. 47 Number of address bytes to write in read transaction. 48STATUS 0x9 - status reg. 49 Bit 0 - transaction is completed. 50 Bit 4 - ACK/NACK. 51DATAx 0xa - 0x54 - 68 bytes data buffer regs. 52 For write transaction address is specified in four first bytes 53 (DATA1 - DATA4), data starting from DATA4. 54 For read transactions address is sent in a separate transaction and 55 specified in the four first bytes (DATA0 - DATA3). Data is read 56 starting from DATA0. 57=============== === =======================================================================