cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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i2c-protocol.rst (3330B)


      1================
      2The I2C Protocol
      3================
      4
      5This document describes the I2C protocol. Or will, when it is finished :-)
      6
      7Key to symbols
      8==============
      9
     10=============== =============================================================
     11S               Start condition
     12P               Stop condition
     13Rd/Wr (1 bit)   Read/Write bit. Rd equals 1, Wr equals 0.
     14A, NA (1 bit)   Acknowledge (ACK) and Not Acknowledge (NACK) bit
     15Addr  (7 bits)  I2C 7 bit address. Note that this can be expanded as usual to
     16                get a 10 bit I2C address.
     17Comm  (8 bits)  Command byte, a data byte which often selects a register on
     18                the device.
     19Data  (8 bits)  A plain data byte. Sometimes, I write DataLow, DataHigh
     20                for 16 bit data.
     21Count (8 bits)  A data byte containing the length of a block operation.
     22
     23[..]            Data sent by I2C device, as opposed to data sent by the
     24                host adapter.
     25=============== =============================================================
     26
     27
     28Simple send transaction
     29=======================
     30
     31Implemented by i2c_master_send()::
     32
     33  S Addr Wr [A] Data [A] Data [A] ... [A] Data [A] P
     34
     35
     36Simple receive transaction
     37==========================
     38
     39Implemented by i2c_master_recv()::
     40
     41  S Addr Rd [A] [Data] A [Data] A ... A [Data] NA P
     42
     43
     44Combined transactions
     45=====================
     46
     47Implemented by i2c_transfer().
     48
     49They are just like the above transactions, but instead of a stop
     50condition P a start condition S is sent and the transaction continues.
     51An example of a byte read, followed by a byte write::
     52
     53  S Addr Rd [A] [Data] NA S Addr Wr [A] Data [A] P
     54
     55
     56Modified transactions
     57=====================
     58
     59The following modifications to the I2C protocol can also be generated by
     60setting these flags for I2C messages. With the exception of I2C_M_NOSTART, they
     61are usually only needed to work around device issues:
     62
     63I2C_M_IGNORE_NAK:
     64    Normally message is interrupted immediately if there is [NA] from the
     65    client. Setting this flag treats any [NA] as [A], and all of
     66    message is sent.
     67    These messages may still fail to SCL lo->hi timeout.
     68
     69I2C_M_NO_RD_ACK:
     70    In a read message, master A/NA bit is skipped.
     71
     72I2C_M_NOSTART:
     73    In a combined transaction, no 'S Addr Wr/Rd [A]' is generated at some
     74    point. For example, setting I2C_M_NOSTART on the second partial message
     75    generates something like::
     76
     77      S Addr Rd [A] [Data] NA Data [A] P
     78
     79    If you set the I2C_M_NOSTART variable for the first partial message,
     80    we do not generate Addr, but we do generate the start condition S.
     81    This will probably confuse all other clients on your bus, so don't
     82    try this.
     83
     84    This is often used to gather transmits from multiple data buffers in
     85    system memory into something that appears as a single transfer to the
     86    I2C device but may also be used between direction changes by some
     87    rare devices.
     88
     89I2C_M_REV_DIR_ADDR:
     90    This toggles the Rd/Wr flag. That is, if you want to do a write, but
     91    need to emit an Rd instead of a Wr, or vice versa, you set this
     92    flag. For example::
     93
     94      S Addr Rd [A] Data [A] Data [A] ... [A] Data [A] P
     95
     96I2C_M_STOP:
     97    Force a stop condition (P) after the message. Some I2C related protocols
     98    like SCCB require that. Normally, you really don't want to get interrupted
     99    between the messages of one transfer.