cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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ten-bit-addresses.rst (1624B)


      1=====================
      2I2C Ten-bit Addresses
      3=====================
      4
      5The I2C protocol knows about two kinds of device addresses: normal 7 bit
      6addresses, and an extended set of 10 bit addresses. The sets of addresses
      7do not intersect: the 7 bit address 0x10 is not the same as the 10 bit
      8address 0x10 (though a single device could respond to both of them).
      9To avoid ambiguity, the user sees 10 bit addresses mapped to a different
     10address space, namely 0xa000-0xa3ff. The leading 0xa (= 10) represents the
     1110 bit mode. This is used for creating device names in sysfs. It is also
     12needed when instantiating 10 bit devices via the new_device file in sysfs.
     13
     14I2C messages to and from 10-bit address devices have a different format.
     15See the I2C specification for the details.
     16
     17The current 10 bit address support is minimal. It should work, however
     18you can expect some problems along the way:
     19
     20* Not all bus drivers support 10-bit addresses. Some don't because the
     21  hardware doesn't support them (SMBus doesn't require 10-bit address
     22  support for example), some don't because nobody bothered adding the
     23  code (or it's there but not working properly.) Software implementation
     24  (i2c-algo-bit) is known to work.
     25* Some optional features do not support 10-bit addresses. This is the
     26  case of automatic detection and instantiation of devices by their,
     27  drivers, for example.
     28* Many user-space packages (for example i2c-tools) lack support for
     29  10-bit addresses.
     30
     31Note that 10-bit address devices are still pretty rare, so the limitations
     32listed above could stay for a long time, maybe even forever if nobody
     33needs them to be fixed.