cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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irq-redir.rst (2660B)


      1==============================
      2IRQ affinity on IA64 platforms
      3==============================
      4
      507.01.2002, Erich Focht <efocht@ess.nec.de>
      6
      7
      8By writing to /proc/irq/IRQ#/smp_affinity the interrupt routing can be
      9controlled. The behavior on IA64 platforms is slightly different from
     10that described in Documentation/core-api/irq/irq-affinity.rst for i386 systems.
     11
     12Because of the usage of SAPIC mode and physical destination mode the
     13IRQ target is one particular CPU and cannot be a mask of several
     14CPUs. Only the first non-zero bit is taken into account.
     15
     16
     17Usage examples
     18==============
     19
     20The target CPU has to be specified as a hexadecimal CPU mask. The
     21first non-zero bit is the selected CPU. This format has been kept for
     22compatibility reasons with i386.
     23
     24Set the delivery mode of interrupt 41 to fixed and route the
     25interrupts to CPU #3 (logical CPU number) (2^3=0x08)::
     26
     27     echo "8" >/proc/irq/41/smp_affinity
     28
     29Set the default route for IRQ number 41 to CPU 6 in lowest priority
     30delivery mode (redirectable)::
     31
     32     echo "r 40" >/proc/irq/41/smp_affinity
     33
     34The output of the command::
     35
     36     cat /proc/irq/IRQ#/smp_affinity
     37
     38gives the target CPU mask for the specified interrupt vector. If the CPU
     39mask is preceded by the character "r", the interrupt is redirectable
     40(i.e. lowest priority mode routing is used), otherwise its route is
     41fixed.
     42
     43
     44
     45Initialization and default behavior
     46===================================
     47
     48If the platform features IRQ redirection (info provided by SAL) all
     49IO-SAPIC interrupts are initialized with CPU#0 as their default target
     50and the routing is the so called "lowest priority mode" (actually
     51fixed SAPIC mode with hint). The XTP chipset registers are used as hints
     52for the IRQ routing. Currently in Linux XTP registers can have three
     53values:
     54
     55	- minimal for an idle task,
     56	- normal if any other task runs,
     57	- maximal if the CPU is going to be switched off.
     58
     59The IRQ is routed to the CPU with lowest XTP register value, the
     60search begins at the default CPU. Therefore most of the interrupts
     61will be handled by CPU #0.
     62
     63If the platform doesn't feature interrupt redirection IOSAPIC fixed
     64routing is used. The target CPUs are distributed in a round robin
     65manner. IRQs will be routed only to the selected target CPUs. Check
     66with::
     67
     68        cat /proc/interrupts
     69
     70
     71
     72Comments
     73========
     74
     75On large (multi-node) systems it is recommended to route the IRQs to
     76the node to which the corresponding device is connected.
     77For systems like the NEC AzusA we get IRQ node-affinity for free. This
     78is because usually the chipsets on each node redirect the interrupts
     79only to their own CPUs (as they cannot see the XTP registers on the
     80other nodes).