cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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irq-chip-model.rst (5362B)

      1.. SPDX-License-Identifier: GPL-2.0
      2
      3=======================================
      4IRQ chip model (hierarchy) of LoongArch
      5=======================================
      6
      7Currently, LoongArch based processors (e.g. Loongson-3A5000) can only work together
      8with LS7A chipsets. The irq chips in LoongArch computers include CPUINTC (CPU Core
      9Interrupt Controller), LIOINTC (Legacy I/O Interrupt Controller), EIOINTC (Extended
     10I/O Interrupt Controller), HTVECINTC (Hyper-Transport Vector Interrupt Controller),
     11PCH-PIC (Main Interrupt Controller in LS7A chipset), PCH-LPC (LPC Interrupt Controller
     12in LS7A chipset) and PCH-MSI (MSI Interrupt Controller).
     13
     14CPUINTC is a per-core controller (in CPU), LIOINTC/EIOINTC/HTVECINTC are per-package
     15controllers (in CPU), while PCH-PIC/PCH-LPC/PCH-MSI are controllers out of CPU (i.e.,
     16in chipsets). These controllers (in other words, irqchips) are linked in a hierarchy,
     17and there are two models of hierarchy (legacy model and extended model).
     18
     19Legacy IRQ model
     20================
     21
     22In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go
     23to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices
     24interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by HTVECINTC, and then go
     25to LIOINTC, and then CPUINTC::
     26
     27     +-----+     +---------+     +-------+
     28     | IPI | --> | CPUINTC | <-- | Timer |
     29     +-----+     +---------+     +-------+
     30                      ^
     31                      |
     32                 +---------+     +-------+
     33                 | LIOINTC | <-- | UARTs |
     34                 +---------+     +-------+
     35                      ^
     36                      |
     37                +-----------+
     38                | HTVECINTC |
     39                +-----------+
     40                 ^         ^
     41                 |         |
     42           +---------+ +---------+
     43           | PCH-PIC | | PCH-MSI |
     44           +---------+ +---------+
     45             ^     ^           ^
     46             |     |           |
     47     +---------+ +---------+ +---------+
     48     | PCH-LPC | | Devices | | Devices |
     49     +---------+ +---------+ +---------+
     50          ^
     51          |
     52     +---------+
     53     | Devices |
     54     +---------+
     55
     56Extended IRQ model
     57==================
     58
     59In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go
     60to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices
     61interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by EIOINTC, and then go to
     62to CPUINTC directly::
     63
     64          +-----+     +---------+     +-------+
     65          | IPI | --> | CPUINTC | <-- | Timer |
     66          +-----+     +---------+     +-------+
     67                       ^       ^
     68                       |       |
     69                +---------+ +---------+     +-------+
     70                | EIOINTC | | LIOINTC | <-- | UARTs |
     71                +---------+ +---------+     +-------+
     72                 ^       ^
     73                 |       |
     74          +---------+ +---------+
     75          | PCH-PIC | | PCH-MSI |
     76          +---------+ +---------+
     77            ^     ^           ^
     78            |     |           |
     79    +---------+ +---------+ +---------+
     80    | PCH-LPC | | Devices | | Devices |
     81    +---------+ +---------+ +---------+
     82         ^
     83         |
     84    +---------+
     85    | Devices |
     86    +---------+
     87
     88ACPI-related definitions
     89========================
     90
     91CPUINTC::
     92
     93  ACPI_MADT_TYPE_CORE_PIC;
     94  struct acpi_madt_core_pic;
     95  enum acpi_madt_core_pic_version;
     96
     97LIOINTC::
     98
     99  ACPI_MADT_TYPE_LIO_PIC;
    100  struct acpi_madt_lio_pic;
    101  enum acpi_madt_lio_pic_version;
    102
    103EIOINTC::
    104
    105  ACPI_MADT_TYPE_EIO_PIC;
    106  struct acpi_madt_eio_pic;
    107  enum acpi_madt_eio_pic_version;
    108
    109HTVECINTC::
    110
    111  ACPI_MADT_TYPE_HT_PIC;
    112  struct acpi_madt_ht_pic;
    113  enum acpi_madt_ht_pic_version;
    114
    115PCH-PIC::
    116
    117  ACPI_MADT_TYPE_BIO_PIC;
    118  struct acpi_madt_bio_pic;
    119  enum acpi_madt_bio_pic_version;
    120
    121PCH-MSI::
    122
    123  ACPI_MADT_TYPE_MSI_PIC;
    124  struct acpi_madt_msi_pic;
    125  enum acpi_madt_msi_pic_version;
    126
    127PCH-LPC::
    128
    129  ACPI_MADT_TYPE_LPC_PIC;
    130  struct acpi_madt_lpc_pic;
    131  enum acpi_madt_lpc_pic_version;
    132
    133References
    134==========
    135
    136Documentation of Loongson-3A5000:
    137
    138  https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-3A5000-usermanual-1.02-CN.pdf (in Chinese)
    139
    140  https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-3A5000-usermanual-1.02-EN.pdf (in English)
    141
    142Documentation of Loongson's LS7A chipset:
    143
    144  https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-7A1000-usermanual-2.00-CN.pdf (in Chinese)
    145
    146  https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-7A1000-usermanual-2.00-EN.pdf (in English)
    147
    148.. Note::
    149    - CPUINTC is CSR.ECFG/CSR.ESTAT and its interrupt controller described
    150      in Section 7.4 of "LoongArch Reference Manual, Vol 1";
    151    - LIOINTC is "Legacy I/OInterrupts" described in Section 11.1 of
    152      "Loongson 3A5000 Processor Reference Manual";
    153    - EIOINTC is "Extended I/O Interrupts" described in Section 11.2 of
    154      "Loongson 3A5000 Processor Reference Manual";
    155    - HTVECINTC is "HyperTransport Interrupts" described in Section 14.3 of
    156      "Loongson 3A5000 Processor Reference Manual";
    157    - PCH-PIC/PCH-MSI is "Interrupt Controller" described in Section 5 of
    158      "Loongson 7A1000 Bridge User Manual";
    159    - PCH-LPC is "LPC Interrupts" described in Section 24.3 of
    160      "Loongson 7A1000 Bridge User Manual".