cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

buddha-driver.rst (7902B)


      1=====================================
      2Amiga Buddha and Catweasel IDE Driver
      3=====================================
      4
      5The Amiga Buddha and Catweasel IDE Driver (part of ide.c) was written by
      6Geert Uytterhoeven based on the following specifications:
      7
      8------------------------------------------------------------------------
      9
     10Register map of the Buddha IDE controller and the
     11Buddha-part of the Catweasel Zorro-II version
     12
     13The Autoconfiguration has been implemented just as Commodore
     14described  in  their  manuals, no tricks have been used (for
     15example leaving some address lines out of the equations...).
     16If you want to configure the board yourself (for example let
     17a  Linux  kernel  configure the card), look at the Commodore
     18Docs.  Reading the nibbles should give this information::
     19
     20  Vendor number: 4626 ($1212)
     21  product number: 0 (42 for Catweasel Z-II)
     22  Serial number: 0
     23  Rom-vector: $1000
     24
     25The  card  should be a Z-II board, size 64K, not for freemem
     26list, Rom-Vektor is valid, no second Autoconfig-board on the
     27same card, no space preference, supports "Shutup_forever".
     28
     29Setting  the  base address should be done in two steps, just
     30as  the Amiga Kickstart does:  The lower nibble of the 8-Bit
     31address is written to $4a, then the whole Byte is written to
     32$48, while it doesn't matter how often you're writing to $4a
     33as  long as $48 is not touched.  After $48 has been written,
     34the  whole card disappears from $e8 and is mapped to the new
     35address just written.  Make sure $4a is written before $48,
     36otherwise your chance is only 1:16 to find the board :-).
     37
     38The local memory-map is even active when mapped to $e8:
     39
     40==============  ===========================================
     41$0-$7e		Autokonfig-space, see Z-II docs.
     42
     43$80-$7fd	reserved
     44
     45$7fe		Speed-select Register: Read & Write
     46		(description see further down)
     47
     48$800-$8ff	IDE-Select 0 (Port 0, Register set 0)
     49
     50$900-$9ff	IDE-Select 1 (Port 0, Register set 1)
     51
     52$a00-$aff	IDE-Select 2 (Port 1, Register set 0)
     53
     54$b00-$bff	IDE-Select 3 (Port 1, Register set 1)
     55
     56$c00-$cff	IDE-Select 4 (Port 2, Register set 0,
     57                Catweasel only!)
     58
     59$d00-$dff	IDE-Select 5 (Port 3, Register set 1,
     60		Catweasel only!)
     61
     62$e00-$eff	local expansion port, on Catweasel Z-II the
     63		Catweasel registers are also mapped here.
     64		Never touch, use multidisk.device!
     65
     66$f00		read only, Byte-access: Bit 7 shows the
     67		level of the IRQ-line of IDE port 0.
     68
     69$f01-$f3f	mirror of $f00
     70
     71$f40		read only, Byte-access: Bit 7 shows the
     72		level of the IRQ-line of IDE port 1.
     73
     74$f41-$f7f	mirror of $f40
     75
     76$f80		read only, Byte-access: Bit 7 shows the
     77		level of the IRQ-line of IDE port 2.
     78		(Catweasel only!)
     79
     80$f81-$fbf	mirror of $f80
     81
     82$fc0		write-only: Writing any value to this
     83		register enables IRQs to be passed from the
     84		IDE ports to the Zorro bus. This mechanism
     85		has been implemented to be compatible with
     86		harddisks that are either defective or have
     87		a buggy firmware and pull the IRQ line up
     88		while starting up. If interrupts would
     89		always be passed to the bus, the computer
     90		might not start up. Once enabled, this flag
     91		can not be disabled again. The level of the
     92		flag can not be determined by software
     93		(what for? Write to me if it's necessary!).
     94
     95$fc1-$fff	mirror of $fc0
     96
     97$1000-$ffff	Buddha-Rom with offset $1000 in the rom
     98		chip. The addresses $0 to $fff of the rom
     99		chip cannot be read. Rom is Byte-wide and
    100		mapped to even addresses.
    101==============  ===========================================
    102
    103The  IDE ports issue an INT2.  You can read the level of the
    104IRQ-lines  of  the  IDE-ports by reading from the three (two
    105for  Buddha-only)  registers  $f00, $f40 and $f80.  This way
    106more  than one I/O request can be handled and you can easily
    107determine  what  driver  has  to serve the INT2.  Buddha and
    108Catweasel  expansion  boards  can issue an INT6.  A separate
    109memory  map  is available for the I/O module and the sysop's
    110I/O module.
    111
    112The IDE ports are fed by the address lines A2 to A4, just as
    113the  Amiga  1200  and  Amiga  4000  IDE ports are.  This way
    114existing  drivers  can be easily ported to Buddha.  A move.l
    115polls  two  words  out of the same address of IDE port since
    116every  word  is  mirrored  once.  movem is not possible, but
    117it's  not  necessary  either,  because  you can only speedup
    11868000  systems  with  this  technique.   A 68020 system with
    119fastmem is faster with move.l.
    120
    121If you're using the mirrored registers of the IDE-ports with
    122A6=1,  the Buddha doesn't care about the speed that you have
    123selected  in  the  speed  register (see further down).  With
    124A6=1  (for example $840 for port 0, register set 0), a 780ns
    125access  is being made.  These registers should be used for a
    126command   access   to  the  harddisk/CD-Rom,  since  command
    127accesses  are Byte-wide and have to be made slower according
    128to the ATA-X3T9 manual.
    129
    130Now  for the speed-register:  The register is byte-wide, and
    131only  the  upper  three  bits are used (Bits 7 to 5).  Bit 4
    132must  always  be set to 1 to be compatible with later Buddha
    133versions  (if  I'll  ever  update this one).  I presume that
    134I'll  never use the lower four bits, but they have to be set
    135to 1 by definition.
    136
    137The  values in this table have to be shifted 5 bits to the
    138left and or'd with $1f (this sets the lower 5 bits).
    139
    140All  the timings have in common:  Select and IOR/IOW rise at
    141the  same  time.   IOR  and  IOW have a propagation delay of
    142about  30ns  to  the clocks on the Zorro bus, that's why the
    143values  are no multiple of 71.  One clock-cycle is 71ns long
    144(exactly 70,5 at 14,18 Mhz on PAL systems).
    145
    146value 0 (Default after reset)
    147  497ns Select (7 clock cycles) , IOR/IOW after 172ns (2 clock cycles)
    148  (same timing as the Amiga 1200 does on it's IDE port without
    149  accelerator card)
    150
    151value 1
    152  639ns Select (9 clock cycles), IOR/IOW after 243ns (3 clock cycles)
    153
    154value 2
    155  781ns Select (11 clock cycles), IOR/IOW after 314ns (4 clock cycles)
    156
    157value 3
    158  355ns Select (5 clock cycles), IOR/IOW after 101ns (1 clock cycle)
    159
    160value 4
    161  355ns Select (5 clock cycles), IOR/IOW after 172ns (2 clock cycles)
    162
    163value 5
    164  355ns Select (5 clock cycles), IOR/IOW after 243ns (3 clock cycles)
    165
    166value 6
    167  1065ns Select (15 clock cycles), IOR/IOW after 314ns (4 clock cycles)
    168
    169value 7
    170  355ns Select, (5 clock cycles), IOR/IOW after 101ns (1 clock cycle)
    171
    172When accessing IDE registers with A6=1 (for example $84x),
    173the timing will always be mode 0 8-bit compatible, no matter
    174what you have selected in the speed register:
    175
    176781ns select, IOR/IOW after 4 clock cycles (=314ns) aktive.
    177
    178All  the  timings with a very short select-signal (the 355ns
    179fast  accesses)  depend  on the accelerator card used in the
    180system:  Sometimes two more clock cycles are inserted by the
    181bus  interface,  making  the  whole access 497ns long.  This
    182doesn't  affect  the  reliability  of the controller nor the
    183performance  of  the  card,  since  this doesn't happen very
    184often.
    185
    186All  the  timings  are  calculated  and  only  confirmed  by
    187measurements  that allowed me to count the clock cycles.  If
    188the  system  is clocked by an oscillator other than 28,37516
    189Mhz  (for  example  the  NTSC-frequency  28,63636 Mhz), each
    190clock  cycle is shortened to a bit less than 70ns (not worth
    191mentioning).   You  could think of a small performance boost
    192by  overclocking  the  system,  but  you would either need a
    193multisync  monitor,  or  a  graphics card, and your internal
    194diskdrive would go crazy, that's why you shouldn't tune your
    195Amiga this way.
    196
    197Giving  you  the  possibility  to  write  software  that  is
    198compatible  with both the Buddha and the Catweasel Z-II, The
    199Buddha  acts  just  like  a  Catweasel  Z-II  with no device
    200connected  to  the  third  IDE-port.   The IRQ-register $f80
    201always  shows a "no IRQ here" on the Buddha, and accesses to
    202the  third  IDE  port  are  going into data's Nirwana on the
    203Buddha.
    204
    205Jens Schönfeld february 19th, 1997
    206
    207updated may 27th, 1997
    208
    209eMail: sysop@nostlgic.tng.oche.de