cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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booting.rst (1072B)


      1.. SPDX-License-Identifier: GPL-2.0
      2
      3BMIPS DeviceTree Booting
      4------------------------
      5
      6  Some bootloaders only support a single entry point, at the start of the
      7  kernel image.  Other bootloaders will jump to the ELF start address.
      8  Both schemes are supported; CONFIG_BOOT_RAW=y and CONFIG_NO_EXCEPT_FILL=y,
      9  so the first instruction immediately jumps to kernel_entry().
     10
     11  Similar to the arch/arm case (b), a DT-aware bootloader is expected to
     12  set up the following registers:
     13
     14         a0 : 0
     15
     16         a1 : 0xffffffff
     17
     18         a2 : Physical pointer to the device tree block (defined in chapter
     19         II) in RAM.  The device tree can be located anywhere in the first
     20         512MB of the physical address space (0x00000000 - 0x1fffffff),
     21         aligned on a 64 bit boundary.
     22
     23  Legacy bootloaders do not use this convention, and they do not pass in a
     24  DT block.  In this case, Linux will look for a builtin DTB, selected via
     25  CONFIG_DT_*.
     26
     27  This convention is defined for 32-bit systems only, as there are not
     28  currently any 64-bit BMIPS implementations.